H01L21/306

Semiconductor device

A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

SUBSTRATE PROCESSING APPARATUS
20180012778 · 2018-01-11 ·

In a substrate processing apparatus, a cup part is moved in an up-down direction to cause a cup exhaust port to selectively overlap a first chamber exhaust port or a second chamber exhaust port. In the state in which the cup exhaust port overlaps the first chamber exhaust port, gas in the cup part is discharged through the cup exhaust port and the first chamber exhaust port by a first exhaust mechanism. In the state in which the cup exhaust port overlaps the second chamber exhaust port, the gas in the cup part is discharged through the cup exhaust port and the second chamber exhaust port by a second exhaust mechanism. In this way, an exhaust mechanism for exhausting gas from the cup part can be easily switched between the first exhaust mechanism and the second exhaust mechanism.

Automatic sampling of hot phosphoric acid for the determination of chemical element concentrations and control of semiconductor processes

Systems and methods for automatic sampling of a sample for the determination of chemical element concentrations and control of semiconductor processes are described. A system embodiment includes a remote sampling system configured to collect a sample of phosphoric acid at a first location, the remote sampling system including a remote valve having a holding loop coupled thereto; and an analysis system configured for positioning at a second location remote from the first location, the analysis system coupled to the remote valve via a transfer line, the analysis system including an analysis device configured to determine a concentration of one or more components of the sample of phosphoric acid and including a sample pump at the second location configured to introduce the sample from the holding loop into the transfer line for analysis by the analysis device.

ADVANCED PROCESS CONTROL METHODS FOR PROCESS-AWARE DIMENSION TARGETING

Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However, instead of performing APC based directly on the actual parameter value, APC is performed based on an adjusted parameter value. Specifically, an offset amount (which is previously determined based on an average of a distribution of parameter values across all of the features) is applied to the actual parameter value to acquire an adjusted parameter value, which better represents the majority of features in the pattern. Performing this APC method minimizes dimension variations from pattern to pattern each time the same pattern is generated on another region of the same wafer or on a different wafer using the particular process.

GaN-on-Si SEMICONDUCTOR DEVICE STRUCTURES FOR HIGH CURRENT/ HIGH VOLTAGE LATERAL GaN TRANSISTORS AND METHODS OF FABRICATION THEREOF
20180012770 · 2018-01-11 ·

A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

Detecting an excursion of a CMP component using time-based sequence of images and machine learning

Monitoring operations of a polishing system includes obtaining a time-based sequence of reference images of a component of the polishing system performing operations during a test operation of the polishing system, receiving from a camera a time-based sequence of monitoring images of an equivalent component of an equivalent polishing system performing operations during polishing of a substrate, determining a difference value for the time-based sequence of monitoring images by comparing the time-based sequence of reference images to the time-based sequence of monitoring image using an image processing algorithm, determining whether the difference value exceeds a threshold, and in response to determining the difference value exceeds the threshold, indicating an excursion.

PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING A PHASE OF FORMING TRENCHES IN A SUBSTRATE AND CORRESPONDING INTEGRATED CIRCUIT

Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

ETCHING LIQUID FOR TITANIUM AND/OR TITANIUM ALLOY, METHOD FOR ETCHING TITANIUM AND/OR TITANIUM ALLOY WITH USE OF SAID ETCHING LIQUID, AND METHOD FOR PRODUCING SUBSTRATE WITH USE OF SAID ETCHING LIQUID

An etching method for quickly removing a seed layer that is formed of titanium and/or a titanium alloy, while suppressing dissolution of other metals from copper wiring lines and the like, for continuous and stable processing; and a composition which is used for this etching method. The composition comprises, based on a total amount of the composition, 0.01 to 0.23% by mass hydrogen peroxide, 0.2 to 3% by mass fluoride, 0.0005 to 0.025% by mass of a halide ion other than a fluoride ion, and water. A method for using the composition to produce a substrate is also described.

WAFER PROCESSING TEMPORARY ADHESIVE, WAFER LAMINATE, THIN WAFER MANUFACTURING METHOD

Provided are: a wafer processing temporary adhesive that is for temporarily adhering a wafer to a support and that comprises a thermosetting resin composition containing a non-functional organopolysiloxane; a wafer laminate; and a thin wafer manufacturing method.

Semiconductor device including fin structures and manufacturing method thereof

A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.