Provided are a cleaning agent and a preparation method and the use thereof. The cleaning agent is prepared from the following raw materials comprising the following mass fraction of components: 0.5%-20% of an oxidant containing iodine, 0.5%-20% of an etchant containing boron, 1%-50% of a pyrrolidinone solvent, 1%-20% of a corrosion inhibitor, 0.01%-5% of a metal ion-free surfactant, and water, with the sum of the mass fraction of each component being 100%, the pH of the cleaning agent is 7.5-13.5, and the corrosion inhibitor is one or more of a benzotriazole corrosion inhibitor, a hydrazone corrosion inhibitor, a carbazone corrosion inhibitor and a thiocarbohydrazone corrosion inhibitor. The cleaning agent can efficiently remove nitrides from hard mask residues with little effects on metals and low-κ dielectric materials, and has a good selectivity.

Nanotwinned copper and non-nanotwinned copper may be electroplated to form mixed crystal structures such as 2-in-1 copper via and RDL structures or 2-in-1 copper via and pillar structures. Nanotwinned copper may be electroplated on a non-nanotwinned copper layer by pretreating a surface of the non-nanotwinned copper layer with an oxidizing agent or other chemical reagent. Alternatively, nanotwinned copper may be electroplated to partially fill a recess in a dielectric layer, and non-nanotwinned copper may be electroplated over the nanotwinned copper to fill the recess. Copper overburden may be subsequently removed.

The present disclosure provides a module including a circuit board, a first component and a second component. The circuit board includes a first side and a second side opposite to each other and includes a first plane and second plane disposed on the first side. A first height difference is formed between the first plane and the second plane. The first component and the second component are disposed on the first plane and the second plane, respectively. The first component and the second component include a first contact surface and a second contact surface, respectively. The first contact surface and the second contact surface are coplanar with a first surface of the module. It benefits to reduce the design complexity of a heat-transfer component, and enhance the heat dissipation capability and the overall power density of the module simultaneously.

In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.

A three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure. A first semiconductor structure includes a first substrate, and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed over the first semiconductor structure, and the second semiconductor structure includes a second substrate, and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.

A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.

Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity and low-photosensitivity photoresist are applied to a substrate and exposed at the same time with use of a dual-tone mask. After being developed, one photoresist forms an overhang over a sheltered region. The mold formed by the photoresists is filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the sheltered region forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.

A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure. The memory array region further comprises vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures, transistor structures, each transistor structure operably coupled to a capacitor structure and to one of the conductive structures of the levels of conductive structures, and a conductive pillar structure vertically extending through the transistor structures. The first microelectronic device further comprises conductive contact structures in electrical communication with the levels of conductive structures at steps of the staircase structures. The second microelectronic device comprises control logic devices configured to effectuate at least a portion of control operations for the vertical stacks of memory cells, conductive interconnect structures vertically extending through an oxide material and in electrical communication with the conductive contact structures, and an additional conductive interconnect structure vertically extending through the oxide material and in electrical communication with the conductive pillar structure of the at least one of the vertical stacks of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.