A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, an Al-based oxide film interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.

A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.

To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parrallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

A structure for an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a high EM-resistant conductive material. The fuse element is comprised of low EM-resistant conductive material.

A semiconductor device includes a first lower line and a second lower line on a substrate, the first and second lower lines extending in a first direction, being adjacent to each other, and being spaced apart along a second direction, orthogonal the first direction, an airgap between the first and second lower lines and spaced therefrom along the second direction, a first insulating spacer on a side wall of the first lower line facing the second lower line, wherein a distance from the first airgap to the first lower line along the second direction is equal to or greater than an overlay specification of a design rule of the semiconductor device, and a second insulating spacer between the airgap and the second lower line.

In a method of manufacturing a semiconductor device, a first insulating interlayer and a sacrificial layer is sequentially formed on a substrate. The sacrificial layer is partially removed to form a first opening exposing an upper surface of the first insulating interlayer. An insulating liner including silicon oxide is conformally formed on the exposed upper surface of the first insulating interlayer and a sidewall of the first opening. At least a portion of the insulating liner on the upper surface of the first insulating interlayer and a portion of the first insulating interlayer thereunder are removed to form a second opening connected to the first opening. A self-forming barrier (SFB) pattern is formed on a sidewall of the second opening and the insulating liner. A wiring structure is formed to fill the first and second openings. After the sacrificial layer is removed, a second insulating interlayer is formed.

A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

A via opening is provided in an interconnect dielectric material. Prior to line opening formation, a continuous layer of a sacrificial material is formed lining the entirety of the via opening. An organic planarization layer (OPL) and a photoresist that contains a line pattern are formed above the interconnect dielectric material. The line pattern is then transferred into an upper portion of the interconnect dielectric material, while maintaining a portion of the OPL and a portion of the continuous layer of sacrificial material within a lower portion of the via opening. The remaining portions of the OPL and the sacrificial material are then removed from the bottom portion of the via opening. A combined via opening/line opening is provided in which the via opening has a well controlled profile/geometry. An interconnect metal or metal alloy can then be formed into the combined via opening/line opening.