An electrostatic discharge (ESD) protection device including a silicon controlled rectifier and a diode string arranged along a first direction is provided. The silicon controlled rectifier includes an anode and a cathode disposed separately from each other. The anode and the cathode respectively include doped regions. The doped regions in the anode are arranged along a second direction. The doped regions in the cathode are arranged along the second direction. The first direction intersects the second direction.

An electrostatic discharge (ESD) protection device including a silicon controlled rectifier and a diode string arranged along a first direction is provided. The silicon controlled rectifier includes an anode and a cathode disposed separately from each other. The anode and the cathode respectively include doped regions. The doped regions in the anode are arranged along a second direction. The doped regions in the cathode are arranged along the second direction. The first direction intersects the second direction.

A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.

A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

The present disclosure relates to semiconductor structures and, more particularly, to heater terminal contacts, methods of operation and methods of manufacture. The structure includes: a heterojunction bipolar transistor having a collector, sub-collector region, emitter and base region; and heater terminal contacts electrically coupled to the sub-collector region.

A power semiconductor device includes a high voltage unit configured to output a high voltage, a low voltage unit configured to output a low voltage, a capacitor electrically connected to the high voltage unit and supplying power to the high voltage unit while the high voltage is output, a switching unit electrically connected to the high voltage unit and the capacitor and configured to connect the capacitor to a driving power source to charge the capacitor while the low voltage is output and to prevent the high voltage unit from being electrically connected to the driving power source while the high voltage is output, and a resistance unit electrically connected between the switching unit and the high voltage unit and configured to drop the high voltage to a voltage lower than a breakdown voltage of the switching unit while the high voltage is output.