A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

In a semiconductor device including a resistance element, an electrostatic protection element, including a parasitic bipolar transistor having the resistance element as a component, is provided. That is, instead of providing a dedicated electrostatic protection element in a semiconductor device, a function as an electrostatic protection element is also achieved by using a resistance element provided in a semiconductor device.

In one embodiment, a RESURF structure between a source and a drain in a lateral MOSFET is formed in a trench having a flat bottom surface and angled sidewalls toward the source. Alternating P and N-type layers are epitaxially grown in the trench, and their charges balanced to achieve a high breakdown voltage. In the area of the source, the ends of the P and N-layers angle upward to the surface under the lateral gate and contact the body region. Thus, for an N-channel MOSFET, a positive gate voltage above the threshold forms a channel between the source and the N-layers in the RESURF structure as well as creates an inversion of the ends of the P-layers near the surface for low on-resistance. In another embodiment, the RESURF structure is vertically corrugated by being formed around trenches, thus extending the length of the RESURF structure for a higher breakdown voltage.

A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive electrical current from an external source. The base is configured to conduct the electrical current from the collector to the emitter. The base is disposed at the top surface of the transistor and laterally between the emitter and the collector. The collector is configured to attract and collect minority carriers from the base. The cathode of the first conductivity type is surrounded by the base and disposed between the emitter and the collector, and the cathode is configured to suppress a lateral flow of the minority carriers from the base to the collector.

A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.

A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.

A semiconductor device is provided, in which a loss of a sensing element is small. A semiconductor device including a semiconductor substrate is provided, the semiconductor device including: an upper-surface electrode that is provided on an upper surface of the semiconductor substrate; a sensing electrode that is provided on the upper surface of the semiconductor substrate and is separated from the upper-surface electrode; a lower-surface electrode that is provided on a lower surface of the semiconductor substrate; a main transistor portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; a main diode portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; and a sense diode portion that is provided to the semiconductor substrate and is connected to the sensing electrode and the lower-surface electrode.

A circuit includes a first transistor, a second transistor and a first resistive load. The first transistor has a first terminal coupled to a first reference voltage terminal, a second terminal coupled to a second reference voltage terminal, and a control terminal coupled to the first reference voltage terminal. The second transistor has a first terminal coupled to the second reference voltage terminal, a second terminal coupled to the first reference voltage terminal and the control terminal of the first transistor, and a control terminal coupled to the second reference voltage terminal and the second terminal of the first transistor. The first transistor further comprises a third terminal coupled to the second reference voltage terminal through the first resistive load.