An epitaxial wafer includes an epitaxial layer disposed on a substrate. The epitaxial layer includes a first semiconductor layer disposed on the substrate and a second semiconductor layer disposed on the first semiconductor layer and having a thickness that is thicker than that of the first semiconductor layer. A surface defect density of the second semiconductor layer is 0.1/cm.sup.2 or less.

A method for manufacturing an LDMOS device includes: forming STI in a substrate; forming a well region in the substrate; forming a body region at one end of the well region, and forming a drift region at the other end of the well region; forming a gate dielectric layer on the substrate; forming a gate structure; forming a drain region in the drift region, and forming a source region in the body region; forming a salicide block layer, wherein the salicide block layer is composed of stacked dielectric layer and conductive layer, the salicide block layer covers the drift region between the gate structure and the drain region, and the salicide block layer extends above the gate structure; forming salicides on the tops of the drain region, the source region, and the gate structure; depositing an interlayer dielectric layer; and forming contacts in the interlayer dielectric layer.

A fin-shaped field-effect transistor (finFET) device is provided. The finFET device includes a substrate material with a first surface and a bottom surface. The finFET device also includes a well region formed in the substrate material. The well region may include a first type of dopant. The finFET device also includes a fin structure disposed on the first surface of the substrate material. A portion of the fin structure may include the first type of dopant. The finFET device also includes an oxide material disposed on the first surface of the substrate material and adjacent to the portion of the fin structure. The finFET device also includes a first epitaxial material disposed over a portion of the fin structure. The first epitaxial material may include a second type of dopant.

A high voltage device for use as a lower switch in a power stage of a switching regulator includes at least one lateral diffused metal oxide semiconductor (LDMOS) device and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well, a body region, a gate, a source, and a drain. The SBD includes a Schottky metal layer and a Schottky semiconductor layer. The Schottky metal layer is electrically connected to the source, and the Schottky semiconductor layer is in contact with the well.

A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.

A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.

A semiconductor device includes a first common source/drain and a second common source/drain spaced apart from each other in a first direction; a first channel structure between the first common source/drain and the second common source/drain, and a second channel structure between the first common source/drain and the second common source/drain and spaced apart from the first channel structure in a vertical direction; a first gate structure surrounding an upper surface, a lower surface, and side surfaces of the first channel structure; and a second gate structure surrounding an upper surface, a lower surface, and side surfaces of the second channel structure, and spaced apart from the first gate structure, wherein a level of the second channel structure is higher than a level of the first channel structure.

A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.

The present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of isolation structures within a substrate. The substrate is selectively etched to form a gate base recess within the substrate. The plurality of isolation structures are selectively etched to form a plurality of gate extension trenches extending outward from the gate base recess; forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and forming a source region and a drain region on opposing sides of the gate electrode.

A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.