A method of manufacturing a semiconductor device includes: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure including alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and forming a gate above the diffusion barrier structure.

A diffused field-effect transistor (FET) and a method of fabricating same are disclosed. The diffused FET is dually optimized in voltage resistance by incorporating both a trench isolation structure and a thick second oxide layer and thus has a more significantly improved breakdown voltage. With the thick second oxide layer ensuring suitable voltage resistance of the transistor device, its on-resistance can be reduced either by reducing the size of the trench isolation structure or increasing an ion dopant concentration of a drift region. As such, a good tradeoff between voltage resistance and on-resistance is achievable.

A semiconductor device is provided that includes an insulated gate field effect transistor series connected with a FET having several parallel conductive layers, a substrate of first conductivity type extending under both transistors, and a first layer of a second conductivity type overlies the substrate. Above this first layer are several conductive layers with channels formed by several of the first conductivity type doped epitaxial layers with layers of a first conductivity type on both sides. The uppermost layer of the device may be substantially thicker than the directly underlying parallel conductive layers. The JFET is isolated with deep poly trenches of second conductivity type on the source side. The insulated gate field effect transistor is isolated with deep poly trenches of the first conductivity type on both sides. A further isolated region is isolated with deep poly trenches of the first conductivity type on both sides.

A semiconductor device includes a semiconductor layer having first and second planes; a first semiconductor region of a first conductivity type; second and third semiconductor regions of a second conductivity type between the first semiconductor region and the first plane; a fourth semiconductor region of a first conductivity type between the second semiconductor region and the first plane; a fifth semiconductor region of a first conductivity type between the third semiconductor region and the first plane; first and second trenches between the fourth and fifth semiconductor regions and over from the second to third semiconductor region; a sixth semiconductor region between the second and third semiconductor regions and between the first and second trenches; a seventh semiconductor region of a second conductivity type between the first trench and the first semiconductor region and contacting the second and third semiconductor regions; a first and second gate electrode in the trenches.

A fin-shaped field-effect transistor (finFET) device is provided. The finFET device includes a substrate material with a first surface and a bottom surface. The finFET device also includes a well region formed in the substrate material. The well region may include a first type of dopant. The finFET device also includes a fin structure disposed on the first surface of the substrate material. A portion of the fin structure may include the first type of dopant. The finFET device also includes an oxide material disposed on the first surface of the substrate material and adjacent to the portion of the fin structure. The finFET device also includes a first epitaxial material disposed over a portion of the fin structure. The first epitaxial material may include a second type of dopant.

The wafer fabrication technique uses an ion implantation process on the back side of the wafer to control the shape of the wafer. At least one first dopant is implanted into a front side of a wafer to dope the wafer. At least one second dopant is implanted into a back side of the wafer in a dopant profile to create a back side structure, where the back side structure controls a shape of the wafer. A blank wafer is provided that has an undoped front side and a form shaping back side structure on the back side. A doped wafer is provided that has a dopant implanted on the front side and a form shaping back side structure on the back side that least partially offsets the strain in the wafer induced by the front side dopant.

A semiconductor device is provided that includes an insulated gate field effect transistor series connected with a FET having several parallel conductive layers, a substrate of first conductivity type extending under both transistors, and a first layer of a second conductivity type overlies the substrate. Above this first layer are several conductive layers with channels formed by several of the first conductivity type doped epitaxial layers with layers of a first conductivity type on both sides. The uppermost layer of the device may be substantially thicker than the directly underlying parallel conductive layers. The JFET is isolated with deep poly trenches of second conductivity type on the source side. The insulated gate field effect transistor is isolated with deep poly trenches of the first conductivity type on both sides. A further isolated region is isolated with deep poly trenches of the first conductivity type on both sides.

A multi-transistor device includes first and second lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistors sharing a first p-type reduced surface field (RESURF) layer and a first drain n+ region. In certain embodiments, the first LDMOS transistor includes a first drift region, the second LDMOS transistor includes a second drift region, and the first and second drift regions are at least partially separated by the first p-type RESURF layer in a thickness direction.

The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.

The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.