A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.

A system and method for creating various dopant concentration profiles using a single implant energy is disclosed. A plurality of implants are performed at the same implant energy but different tilt angles to implant ions at a variety of depths. The result of these implants may be a rectangular profile or a gradient profile. The resulting dopant concentration profile depends on the selection of tilt angles, doses and the number of implants. Varying tilt angle rather than varying implant energy to achieve implants of different depths may significantly improve efficiency and throughput, as the tilt angle can be changed faster than the implant energy can be changed. Additionally, this method may be performed by a number of different semiconductor processing apparatus.

A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.

According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.

An insulated gate bipolar transistor and a preparation method thereof, and an electronic device. The insulated gate bipolar transistor includes: a drift region; an electrode structure on one side of the drift region; and an electric field stop layer arranged on one side of the drift region away from the electrode structure. The electric field stop layer includes a first sublayer and a second sublayer laminated together. The first sublayer is arranged close to the drift region. A junction depth of the first sublayer is greater than a junction depth of the second sublayer. A peak value of a doping concentration of the first sublayer is less than a peak value of a doping concentration of the second sublayer. A slope of a doping concentration curve of the first sublayer is less than a slope of a doping concentration curve of the second sublayer.

A laminate contains a crystal substrate; a middle layer formed on a main surface of the crystal substrate, the middle layer comprising a mixture of an amorphous region in an amorphous phase and a crystal region in a crystal phase having a corundum structure mainly made of a first metal oxide; and a crystal layer formed on the middle layer and having a corundum structure mainly made of a second metal oxide, wherein the crystal region is an epitaxially grown layer from a crystal plane of the crystal substrate.

A semiconductor device includes a semiconductor part, first and second electrodes and a control electrode. The semiconductor part is provided between the first and second electrodes. The control electrode is provided between the semiconductor part and the second electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type, and second, fourth, sixth and seventh layers of a second conductivity type. The second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The fourth and fifth layers are provided between the first layer and the first electrode. The sixth layer surrounds the second and third layers. The seventh layer is provided between the first layer and the first electrode. The seventh layer surrounds the fourth and fifth layers and is apart from the fourth and fifth layers.

A power semiconductor device includes an active region and an edge termination region surrounding the active region. A field plate structure arranged around the active region includes at least one electrically conductive track electrically connected to a first potential of a first load terminal at a first joint and, at a second joint, electrically connected to a second potential of a second load terminal. The track forms at least n crossings, wherein n is greater 5, with a straight virtual line that extends from the active region towards an edge of the edge termination region. The difference in potential between adjacent two crossings increases in at least 50% of the length of the virtual line, and/or the difference in potential within, with respect to the active region, the first 20% of the length of virtual line is less than 10% of the total difference in potential along the virtual line.

A power device includes a semiconductor substrate having first and second current carrying terminals on respective first and second opposing surfaces thereof. A silicided polysilicon temperature sensor and silicided polysilicon gate electrode are provided on the first surface. A source region of first conductivity type and a shielding region of second conductivity type are provided in the semiconductor substrate. The shielding region forms a P-N rectifying junction with the source region, and extends between the silicided polysilicon temperature sensor and the second current carrying terminal. A field oxide insulating region is provided, which extends between the shielding region and the silicided polysilicon temperature sensor.

A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.