The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

A p.sup.-type isolation region is provided at a part between a p-type ground region and a circuit region (a high potential region and an intermediate potential region) in an n-type well region. The p.sup.-type isolation region is electrically connected with a H-VDD pad and an n.sup.+-type drain region of a HVNMOS. The p.sup.-type isolation region has between n.sup.+-type pickup connect regions and between n.sup.+-type drain regions of two of the HVNMOSs, a protruding part (a T-shaped part, an L-shaped part, a partial U-shaped part) or an additional part that protrudes toward a p-ground region.

A cascade arrangement and to a semiconductor module. The cascode arrangement includes: a substrate, a JFET, a MOSFET, and at least one sensor system. A drain terminal of the MOSFET is electrically connected to a source terminal of the JFET and a source terminal of the MOSFET is electrically connected to a gate terminal of the JFET. A first semiconductor layer in which the MOSFET is formed and a second semiconductor layer in which the JFET is formed, are situated stacked on top of one another via a connecting material. Both an electrical and a thermal coupling between the JFET and the MOSFET are implemented via the connecting material. The stacked semiconductor layers are situated on the substrate. The first semiconductor layer includes a first subarea in which the MOSFET is formed and at least one second subarea in which the at least one sensor system is formed.

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.

The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer. The present disclosure provides a PMOS FET with better gate control functionality and a low interface density with the double-gate structure and interface control layer design, in order to meet the requirements of high-performance PMOS transistors.

A semiconductor device has a lateral switching device that includes a channel forming layer, a gate structure portion, a source electrode, a drain electrode, a third semiconductor layer, a fourth semiconductor layer, and a junction gate electrode. The gate structure portion has a gate insulating film provided in a recess portion of the channel forming layer and a MOS gate electrode functioning as a gate electrode of a MOS structure provided on the gate insulating film. The source electrode and the junction gate electrode are coupled through an electrode layer provided on an interlayer insulating film covering the MOS gate electrode. An end of the third semiconductor layer facing the drain electrode protrudes toward the drain electrode from an end of the fourth semiconductor layer facing the drain electrode by a distance in a range of 1 m to 5 m both inclusive.

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

A semiconductor device includes an insulated gate field effect transistor connected in series with a FET. The FET includes parallel conductive layers. A substrate of first conductivity type extends under both transistors, with a first layer of a second conductivity type over the substrate. On this first layer are arranged conductive layers with channels formed by the first conductivity type doped epitaxial layers with layers of a first conductivity type on both sides. The uppermost layer of the device is thicker than the directly underlying several parallel conductive layers. The field effect transistor, JFET, is isolated with deep poly trenches of first conductivity type, DPPT, on the source side of the JFET. The insulated gate field effect transistor is isolated with deep poly DPPT trenches on both sides. A further isolated region with logic and analog control functions is isolated with deep poly DPPT trenches on both sides.