Described is a semiconductor device including a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region, a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region, and a first gate electrode and a second gate electrode disposed spaced apart from the drain region. A maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view.

Provided is a radiation-tolerant unit MOSFET to block a leakage current path caused by a total ionizing dose effect and reduce influence of a current pulse generated due to a single event effect. The radiation-tolerant unit MOSFET includes a poly gate layer for designating a gate region and at least one dummy gate region, a source and a drain, and a P+ layer and a P-active layer for specifying a P+ region to the source and the drain, and a dummy drain allowing application of a voltage. An electronic part that may normally operate is provided even a radiation environment where particle radiation and electromagnetic radiation are present.

A semiconductor device includes a source region configured to provide at least a portion of a MOSFET source of a MOSFET and at least a portion of a JFET source of a JFET. The semiconductor device includes a JFET channel region in series with the source region and a MOSFET channel region of the MOSFET, and disposed between a first JFET gate and a second JFET gate. The semiconductor device includes a JFET drain disposed at least partially between a gate insulator of a gate of the MOSFET and at least a portion of the JFET channel region, and in electrical contact with the first JFET gate and the second JFET gate. Various example implementations of this type of semiconductor device provide a SiC power MOSFET with improved short-circuit capability and durability, with minimal impact on R.sub.DS-ON.

A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.

A semiconductor device includes: an n type layer disposed on a first surface of a substrate; an n+ type region disposed on the n type layer; a trench disposed on the n type layer; a p type region disposed adjacent to a side surface of the trench and extending to a part under a lower surface of the trench; an auxiliary n+ type region disposed under the lower surface of the trench and disposed in the p type region; an auxiliary electrode disposed at the lower surface of the trench; a gate electrode separated from the auxiliary electrode and disposed on the lower surface of the trench; a source electrode disposed on the n+ type region; and a drain electrode disposed at a second surface of the substrate.

A semiconductor device includes an inversion type semiconductor element including: a semiconductor substrate; a first conductive type layer formed on the semiconductor substrate; an electric field blocking layer formed on the first conductive type layer and including a linear shaped portion; a JFET portion formed on the first conductive type layer and having a linear shaped portion; a current dispersion layer formed on the electric field blocking layer and the JFET portion; a deep layer formed on the electric field blocking layer and the JFET portion; a base region formed on the current dispersion layer and the deep layer; a source region formed on the base region; trench gate structures including a gate trench, a gate insulation film, and a gate electrode, and arranged in a stripe shape; an interlayer insulation; a source electrode; and a drain electrode formed on a back surface side of the semiconductor substrate.

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.

Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.