The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.

A semiconductor device includes a graphene film disposed on a substrate and formed of atomic layers of graphene that are stacked, a source electrode and a drain electrode disposed on the graphene film, and a gate electrode disposed on the graphene film between the source electrode and the drain electrode with a gate insulator film interposed between the gate electrode and the graphene film, wherein a first number of the atomic layers of the graphene film in a source region where the source electrode is located and a drain region where the drain electrode is located is greater than a second number of the atomic layers of the graphene film in a channel region where the gate electrode is located.

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO.sub.2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO.sub.2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO.sub.2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO.sub.2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (V.sub.g) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

Described herein are solid-state devices based on graphene in a Field Effect Transistor (FET) structure that emits high frequency Electromagnetic (EM) radiation using one or more DC electric fields and periodic magnetic arrays or periodic nanostructures. A number of devices are described that are capable of generating and emitting electromagnetic radiation.

A thin film transistor and a producing method thereof, and an array substrate, which belong to a technical field of the thin film transistor, can solve a problem of poor performance of a conventional thin film transistor. The producing method of the thin film transistor comprises: S1: forming a gate electrode (11) composed of graphene; S2: forming a gate insulating layer (12) composed of oxidized graphene; S3: forming an active region (13) composed of doped oxidized graphene or doped graphene; S4: forming a source electrode (14) and a drain electrode (15) composed of graphene, wherein, the graphene composing the source electrode (14), the drain electrode (15) and the gate electrode (11) is formed by reducing oxidized graphene, and the doped oxidized graphene or doped graphene composing the active region (13) is formed by treating oxidized graphene.

Methods and systems for emitting light from electrically biased graphene are provided. An exemplary method of generating a light emission from graphene includes suspending a graphene membrane using at least one mechanical clamp and providing a current to the graphene membrane to establish a source-drain bias voltage along the graphene membrane.

The present disclosure provides a pixel driving circuit, an array substrate and a display panel. The pixel driving circuit of the present disclosure includes a switch transistor and N redundant switch transistors, the switch transistor and the N redundant switch transistors are connected in series, a second electrode of an N.sup.th redundant switch transistor is coupled to a first electrode of the switch transistor, and a second electrode of the switch transistor is coupled to a display electrode.

A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the stack structure includes a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer are made of different material. Next, a hard mask is formed on the stack structure and a first spacer adjacent to the hard mask, part of the stack structure is removed; a second spacer is formed adjacent to the first spacer and the stack structure; and a source/drain structure is formed adjacent to two sides of the second spacer.

An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.