A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.

A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

A latch type sense amplifier includes three transistors, a latching device and two capacitors. The two drain/source terminals of the first transistor are connected with a first node and a second node. The gate terminal of the first transistor receives a reference voltage. The two drain/source terminals of the second transistor are connected with the first node and a third node. The gate terminal of the second transistor is connected with a data line. The two drain/source terminals of the third transistor are connected with a first supply voltage and the first node. The gate terminal of the third transistor receives an enable signal. The latching device is connected with the second node and the third node. The first capacitor is connected between gate terminals of the third transistor and the first transistor. The second capacitor is connected between gate terminals of the third transistor and the second transistor.

A non-volatile memory receives a supply voltage. The non-volatile memory includes a reference current generator and a sensing circuit. The reference current generator provides a reference current to the sensing circuit. The reference current generator includes a control voltage generation circuit, a current path selecting circuit and a mirroring circuit. The control voltage generation circuit receives a control signal and generates a control voltage according to the control signal. The current path selecting circuit generates the reference current. A current input terminal of the mirroring circuit receives the reference current. If the control signal is set as a first value, the reference current is changed at a first slope in a range of the supply voltage. If the control signal is set as a second value, the reference current is changed at a second slope in the range of the supply voltage.

A memory cell is connected to a source line, a bit line, a word line, an assist gate line and an erase line. When a program action is performed, a weak programming procedure is first performed on the memory cell, and then a strong programming procedure is performed on the memory cell. When the weak programming procedure is performed, an on voltage is provided to the word line, a first program voltage is provided to the source line, a ground voltage is provided to the bit line, a first assist gate voltage is provided to the assist gate line, and a first erase line voltage is provided to the erase line. When the strong programming procedure is performed, a lower program voltage and a higher assist gate voltage are provided to the memory cell.

A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.

A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.