A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes the following operations. A first integrated circuit component having a fuse structure is received. A second integrated circuit component having an inductor is received. The second integrated circuit component is bonded to the first integrated circuit component. The inductor is electrically connected to the fuse structure, wherein the inductor is electrically connected to a ground through the fuse structure.

A semiconductor structure includes a circuit carrier, a dielectric layer, a conductive terminal, a semiconductor die, and an insulating encapsulation. The circuit carrier includes a first surface and a second surface opposite to each other, a sidewall connected to the first and second surfaces, and an edge between the second surface and the sidewall. The dielectric layer is disposed on the second surface of the circuit carrier and extends to at least cover the edge of the circuit carrier. The conductive terminal is disposed on and partially embedded in the dielectric layer to be connected to the circuit carrier. The semiconductor die encapsulated by the insulating encapsulation is disposed on the first surface of the circuit carrier and electrically coupled to the conductive terminal through the circuit carrier.

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes receiving a first integrated circuit component having a seal ring and a fuse structure, wherein the fuse structure is electrically connected to a ground through the seal ring; receiving a second integrated circuit component having an inductor; bonding the second integrated circuit component to the first integrated circuit component; electrically connecting the inductor to the fuse structure, wherein the inductor is electrically connected to the ground through the fuse structure; and blowing the fuse structure after a treatment.

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes: a first die including: a fuse structure including a pair of conductive segments, wherein the pair of conductive segments are separated by a void and one of the pair of conductive segments is electrically connected to a bonding pad of the first die; and a second die over and bonded to the first die, the second die including an inductor electrically connected to the one of the pair of conductive segments.

An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes the following operations. A first integrated circuit component having a fuse structure is received. A second integrated circuit component having an inductor is received. The second integrated circuit component is bonded to the first integrated circuit component. The inductor is electrically connected to the fuse structure, wherein the inductor is electrically connected to a ground through the fuse structure.

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a circuit carrier, a dielectric layer, a conductive terminal, a semiconductor die, and an insulating encapsulation. The circuit carrier includes a first surface and a second surface opposite to each other, a sidewall connected to the first and second surfaces, and an edge between the first surface and the sidewall. The dielectric layer is disposed on the first surface of the circuit carrier and extends to at least cover the edge of the circuit carrier. The conductive terminal is disposed on and partially embedded in the dielectric layer to be connected to the circuit carrier. The semiconductor die encapsulated by the insulating encapsulation is disposed on the second surface of the circuit carrier and electrically coupled to the conductive terminal through the circuit carrier.

Methods for processing a semiconductor transistor are provided, where the semiconductor transistor includes a substrate, an epitaxial layer, and transistor components that are formed on the epitaxial layer. The method includes: removing a portion of the substrate that is disposed below a portion of the transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer; forming an electrically insulating layer on the exposed portion of the bottom surface of the epitaxial layer; forming a via that extends from a bottom surface of the insulating layer to a bottom surface of one of the transistor components; depositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of one of the transistor components; and applying a solder paste to a bottom surface of the at least one metal layer.

Methods for processing a semiconductor transistor are provided, where the semiconductor transistor includes a substrate, an epitaxial layer, and transistor components that are formed on the epitaxial layer. The method includes: removing a portion of the substrate that is disposed below a portion of the transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer; forming an electrically insulating layer on the exposed portion of the bottom surface of the epitaxial layer; forming a via that extends from a bottom surface of the insulating layer to a bottom surface of one of the transistor components; depositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of one of the transistor components; and applying a solder paste to a bottom surface of the at least one metal layer.

HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT.