A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes: a first die including: a fuse structure including a pair of conductive segments, wherein the pair of conductive segments are separated by a void and one of the pair of conductive segments is electrically connected to a bonding pad of the first die; and a second die over and bonded to the first die, the second die including an inductor electrically connected to the one of the pair of conductive segments.

A method includes forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer, forming a metal layer as a part of the wafer, and forming a transistor comprising a first source/drain region connected to the first integrated circuit devices. The transistor is farther away from the semiconductor substrate than the metal layer. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.

In a package device, wherein integrated circuit devices are bonded to a substrate, stress arising from mechanical strain, CTE mismatch, and the like can be alleviated or eliminated by incorporating stress buffering air gaps into a protective material, such as a gap fill oxide. The air gaps can be formed by tuning and changing deposition parameters during the deposition process and/or by tuning the size and placement of adjacent integrated circuit devices in the package, and/or by forming trenches in the protective material prior to the bonding process.

An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.

A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

Some embodiments relate to an integrated circuit (IC) device including a substrate, a plurality of electrically conductive structures disposed over the substrate and separated from each other, and at least one electrically insulating structure disposed over the substrate and directly contacting each of the plurality of electrically conductive structures. The at least one electrically insulating structure has a thermal conductivity greater than five watts per meter-Kelvin (W/m-K).

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a first die including a fuse structure in a topmost layer of the first die, the fuse structure including a pair of conductive segments, wherein one of the pair of conductive segments is electrically connected to a bonding pad of the first die, wherein the bonding pad is electrically connected to ground; and an inductor electrically connected to the one of the pair of conductive segments.

An apparatus includes a substrate, a cavity within the substrate, and a die within the cavity. The substrate has an exterior surface. The cavity includes a first surface and a second surface opposite the first surface. The die includes a discrete component, a first side, a second side opposite the first side, and conductive features at the first side. In an embodiment, a bond film is between the first surface and the first side. A plurality of conductive vias extend from the exterior surface through the substrate and bond film to the conductive features. In an embodiment, the bond film may be omitted. The plurality of conductive vias extend from the exterior surface through the substrate. The conductive features of the die are coupled with the conductive vias by solder features, and the second side of the die is spaced away from the second surface.

Embodiments disclosed herein include apparatuses with assemblies comprising passive electrical devices that are embedded in a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface coupling the first surface to the second surface. In an embodiment the substrate comprises a passive electrical device. In an embodiment, a pad is on the first surface of the substrate, and a layer contacts the substrate. In an embodiment, the layer directly contacts the first surface and the sidewall surface of the substrate.

A packaged integrated circuit (IC) including a package substrate. The package substrate includes pins; a first metal layer on the pins; a second metal layer on the first metal layer; vias on the second metal layer; an insulation material covering the pins, the first metal layer, the second metal layer, and the vias, and exposing surfaces of the pins and the vias. The packaged IC further includes a semiconductor die on the package substrate, the semiconductor die having a surface opposing the second metal layer; metal posts coupled between the semiconductor die and the exposed surfaces of the vias; and a mold compound covering the semiconductor die and the metal posts, in which the surface is separated from the second metal layer by the insulation material and the mold compound.