In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

A method for forming a semiconductor device includes: forming a trench structure with trenches in an inner region and an edge region of a SiC semiconductor body such that the trench structure extends from a first surface of the semiconductor body through a second semiconductor layer into a first semiconductor layer and such that the trench structure, in the second semiconductor layer, forms mesa regions; and forming at least one transistor cell at least partially in each of the mesa regions in the inner region. Forming each transistor cell includes forming at least one compensation region. Forming the compensation region includes implanting dopant atoms of a second doping type via sidewalls of the trenches into the mesa regions in the inner region. Forming the compensation region in each mesa region in the inner region includes at least partially covering the edge region with an implantation mask.

A capacitor is provided for integration with a MOSFET device(s) formed on the same substrate. The capacitor comprises a first plate including a doped semiconductor layer of a first conductivity type, an insulating layer formed on an upper surface of the doped semiconductor layer, and a second plate including a polysilicon layer formed on an upper surface of the insulating layer. An inversion layer is formed in the doped semiconductor layer, beneath the insulating layer and proximate the upper surface of the doped semiconductor layer, as a function of an applied voltage between the first and second plates of the capacitor. At least one doped region of a second conductivity type, opposite the first conductivity type, is formed in the doped semiconductor layer adjacent to a drain and/or source region of the first conductivity type formed in the MOSFET device. The doped region is electrically connected to the inversion layer.

The present disclosure has an object of providing a silicon carbide semiconductor device with high productivity which prevents characteristic degradation occurring when a large current is applied to a body diode. A structure including a SiC substrate, a buffer layer, and a drift layer is classified into an active region through which a current flows with application of a voltage to the SiC-MOSFET, and a breakdown voltage support region around a periphery of the active region in a plan view. The active region is classified into a first active region in a center portion, and a second active region between the first active region and the breakdown voltage support region in the plan view. Lifetimes of minority carriers in the second active region and the breakdown voltage support region are shorter than that in the first active region.

A cell structure of a silicon carbide MOSFET device, comprising a drift region (3) located on a substrate layer (2), a second conducting type well region (4) and a first JFET region (51) that are located in the drift region (3), an enhancement region located within a surface of the well region (4), a gate insulating layer (8) located on a first conducting type enhancement region (6), the well region (4) and the first JFET region (51) and being in contact therewith at the same time, a gate (9) located on the gate insulating layer, source metal (10) located on the enhancement region, Schottky metal (11) located on a second conducting type enhancement region (7) and the drift region (3), a second JFET region (52) located on a surface of the drift region (3) between the Schottky metals (11), and drain metal (12).

First p.sup.+-type regions are provided directly beneath trenches, separate from a p-type base region and facing bottoms of the trenches in a depth direction. The first p.sup.+-type regions are exposed at the bottoms of the trenches and are in contact with a gate insulating film at the bottoms of the trenches. Second p.sup.+-type regions are each provided between (mesa region) adjacent trenches, separate from the first p.sup.+-type regions and the trenches. Drain-side edges of the second p.sup.+-type regions are positioned closer to a source side than are drain-side edges of the first p.sup.+-type regions. In each mesa region, an n.sup.+-type region is provided separate from the first p.sup.+-type regions and the trenches. The n.sup.+-type regions are adjacent to and face the second p.sup.+-type regions in the depth direction.

A main semiconductor device element has first and second p.sup.+-type high-concentration regions that mitigate electric field applied to bottoms of trenches. The first p.sup.+-type high-concentration regions are provided separate from p-type base regions, face the bottoms of the trenches in a depth direction, and extend in a linear shape in a first direction that is a same direction in which the trenches extend. Between adjacent trenches of the trenches, the second p.sup.+-type high-concentration regions are provided scattered in the first direction, separate from the first p.sup.+-type high-concentration regions and the trenches and in contact with the p-type base regions. Between the second p.sup.+-type high-concentration regions adjacent to one another in the first direction, n-type current spreading regions or n.sup.+-type high-concentration regions having an impurity concentration higher than that of the n-type current spreading regions are provided in contact with the second p.sup.+-type high-concentration regions.

A semiconductor device includes a semiconductor substrate, a body layer, a source region, a drift layer, a drain region, a gate insulating film, and a gate electrode. The semiconductor substrate has an active layer. An element region is included in the active layer and partitioned by a trench isolation portion. The body layer is disposed at a surface layer portion of the active layer. The source region is disposed at a surface layer portion of the body layer. The drift layer is disposed at the surface layer portion of the active layer. The drain region is disposed at a surface layer portion of the drift layer. The gate insulating film is disposed on a surface of the body layer. The gate electrode is disposed on the gate insulating film. One of the source region and the drain region being a high potential region is surrounded by the other one being a low potential region.

A vertical semiconductor transistor is provided that includes: a source region, a drain region, and a body region formed in a semiconductor substrate; wherein the source region and the drain region are doped with a first type dopant; wherein the body region is doped with a second type dopant; and wherein the second type dopant has a doping profile within the body region that varies with distance from the source region.