A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.

A Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes a gate stack comprising a first nitride layer. The first nitride layer is formed on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack includes a polysilicon layer formed from the silicon layer, and a second oxide layer is formed on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer conformingly covers the second oxide layer. A nitride etch-stop layer conformingly covers the second nitride layer.

A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.

A process of forming a gate insulating film in a silicon carbide semiconductor device. The process includes performing a first stage of a nitriding heat treatment by a gas containing oxygen and nitrogen, followed by depositing an oxide film, and then performing a second stage of the nitriding heat treatment by a gas containing nitric oxide and nitrogen. The amount of nitrogen at the treatment starting point of the first stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment starting point of the second stage of the nitriding heat treatment. The amount of nitrogen at the treatment ending point of the second stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment ending point of the first stage of the nitriding heat treatment.

A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

In a silicon carbide semiconductor device in which a contact electrode is formed on a single-crystal silicon carbide semiconductor substrate, a barrier metal (titanium nitride layer) covers an interlayer insulating film in a region other than a contact hole, and a contact electrode of a predetermined electrode material is formed only in a region on the silicon carbide semiconductor substrate in the contact hole opened in the interlayer insulating film on the silicon carbide semiconductor substrate. A top of the barrier metal is covered by a metal electrode (wiring layer) and no nickel metal aggregates are present between the barrier metal and the metal electrode.

A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

A multi-transistor device includes first and second lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistors sharing a first p-type reduced surface field (RESURF) layer and a first drain n+ region. In certain embodiments, the first LDMOS transistor includes a first drift region, the second LDMOS transistor includes a second drift region, and the first and second drift regions are at least partially separated by the first p-type RESURF layer in a thickness direction.

A semiconductor device of the present invention includes a semiconductor region having a first main surface, wherein the semiconductor region includes: alternating n-type pillar layers and p-type pillar layers along the first main surface; a p-type first well layer located within each of the n-type pillar layers at a top surface of the n-type pillar layer; an n-type first source layer located within the first well layer at a top surface of the first well layer; a first side surface dielectric layer located on a side surface in a first trench located at each of boundaries between the n-type pillar layers and the p-type pillar layers, and being in contact with the first well layer and the first source layer; a first bottom surface dielectric layer located on a bottom surface in the first trench, and being at least partially in contact with one of the p-type pillar layers.