The present invention introduces a new shielded gate trench MOSFETs wherein epitaxial layer having special multiple stepped epitaxial (MSE) layers with different doping concentrations decreasing in a direction from substrate to body regions, wherein each of the MSE layers has uniform doping concentration as grown. Specific on-resistance is significantly reduced with the special MSE structure. Moreover, in sore preferred embodiment, an MSO (multiple stepped oxide) structure is applied to the shielded gate structure to further reduce the specific on-resistance and enhance device ruggedness.

Embodiments of processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: depositing, via a first epitaxial growth process, an n-doped silicon material onto a substrate to form an n-doped layer while adjusting a ratio of dopant precursor to silicon precursor so that a dopant concentration of the n-doped layer increases from a bottom of the n-doped layer to a top of the n-doped layer; etching the n-doped layer to form a plurality of trenches having sidewalls that are tapered and a plurality of n-doped pillars therebetween; and filling the plurality of trenches with a p-doped material via a second epitaxial growth process to form a plurality of p-doped pillars.

A power device includes a semiconductor substrate having first and second current carrying terminals on respective first and second opposing surfaces thereof. A silicided polysilicon temperature sensor and silicided polysilicon gate electrode are provided on the first surface. A source region of first conductivity type and a shielding region of second conductivity type are provided in the semiconductor substrate. The shielding region forms a P-N rectifying junction with the source region, and extends between the silicided polysilicon temperature sensor and the second current carrying terminal. A field oxide insulating region is provided, which extends between the shielding region and the silicided polysilicon temperature sensor.

The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.

A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.

The present invention introduces a new shielded gate trench SBR (Super Barrier Rectifier) wherein an epitaxial layer having special MSE (multiple stepped epitaxial) layers with different doping concentrations decreasing in a direction from a substrate to a top surface of the epitaxial layer, wherein each of the MSE layers has an uniform doping concentration as grown. Forward voltage V.sub.f is significantly reduced with the special MSE layers. An integrated circuit comprising a SGT MOSFET and a SBR formed on a single chip obtains benefits of low on-resistance, low reverse recovery time and high avalanche capability from the special MSE layers.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed on the semiconductor substrate and having a first conductivity type impurity concentration higher than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type formed above the first semiconductor layer, a first device region formed in the second semiconductor layer and configured to operate based on a first reference voltage, a second device region formed in the second semiconductor layer and configured to operate based on a second reference voltage, the second device region being spaced apart from the first device region, and a region isolation structure interposed between the first and second device regions and formed in a region extending from a front surface of the second semiconductor layer to the first semiconductor layer so as to electrically isolate the first and second device regions from each other.

First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.

A body diode is energized by inputting a BD energization pulse signal having a predetermined cycle. At the start of energization of the body diode and immediately before termination thereof, an ON signal of a Von measurement pulse signal is input to a high-temperature semiconductor chip at a timing different from that of an ON signal of the BD energization pulse signal, thereby passing a drain-source current through a MOSFET, and a drain-source voltage is measured. Thereafter, energization of the body diode is terminated. At room temperature before and after the energization of the body diode, the drain-source voltage is measured by inputting the ON signal of the Von measurement pulse signal. A semiconductor chip for which a fluctuation amount of the drain-source voltage at a high temperature and a fluctuation amount of the drain-source voltage at room temperature are within predetermined ranges is determined to be a conforming product.

The present application discloses a super junction device, comprising: an N-type redundant epitaxial layer and an N-type buffer layer sequentially formed on an N-type semiconductor substrate; wherein a trench-filling super junction structure is formed on the N-type buffer layer; a backside structure of the super junction device comprises a drain region; the N-type semiconductor substrate is removed in a backside thinning process, and the N-type redundant epitaxial layer is completely or partially removed in the backside thinning process; the resistivity of the N-type semiconductor substrate is 0.1-10 times the resistivity of a top epitaxial layer; the resistivity of the N-type redundant epitaxial layer is 0.1-10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer. The present application further discloses a method for manufacturing a super junction device.