A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

A vertical-conduction MOSFET device, includes: a semiconductor body, having a front side and a back side and having a first conductivity; a trench-gate region; a body region, having the first conductivity; a source region, having a second conductivity; and a drain region, having the second conductivity. The source region, body region, and drain region are aligned with one another along a first direction and define a channel area, which, in a conduction state of the MOSFET device, hosts a conductive channel. The drain region borders on a portion of the semiconductor body having the first conductivity, thus forming a junction diode, which, in an inhibition state of the MOSFET device, is adapted to cause a leakage current to flow outside the channel area.

A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.

A semiconductor device includes: an inversion type semiconductor element that includes: a substrate having a first conductivity type or a second conductivity type; a first conductivity type layer formed on the substrate; a second conductivity type region that is formed on the first conductivity type layer; a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed; a source region that is formed on the second conductivity region; a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film; an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole; a source electrode electrically connected to the source region through the contact hole; and a drain electrode formed on a back side of the substrate.

A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping.

Disclosed is a semiconductor device and a manufacturing method, comprising: forming a pad oxide layer and a silicon nitride layer on a substrate; etching the silicon nitride layer into a plurality of segments; forming an oxide layer, having an up-and-down wave shape, by performing a traditional thermal growth field oxygen method on the semiconductor device by use of the plurality of segments serving as forming-assisted structures; performing traditional processes on the semiconductor device having an up-and-down wavy semiconductor surface, to form a gate oxide layer, a polysilicon layer, and to form a source region and a drain region by implantation The semiconductor device having an up-and-down wavy channel region may be formed by a traditional thermal growth field oxygen method, thus the manufacturing processes are simple, the cost is low, and the completed device may have a larger effective channel width and a lower on-state resistance.

A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Disclosed is a semiconductor device and a manufacturing method, comprising: forming a pad oxide layer and a silicon nitride layer on a substrate; etching the silicon nitride layer into a plurality of segments; forming an oxide layer, having an up-and-down wave shape, by performing a traditional thermal growth field oxygen method on the semiconductor device by use of the plurality of segments serving as forming-assisted structures; performing traditional processes on the semiconductor device having an up-and-down wavy semiconductor surface, to form a gate oxide layer, a polysilicon layer, and to form a source region and a drain region by implantation The semiconductor device having an up-and-down wavy channel region may be formed by a traditional thermal growth field oxygen method, thus the manufacturing processes are simple, the cost is low, and the completed device may have a larger effective channel width and a lower on-state resistance.

A high-voltage semiconductor device includes a MOS device and a resistor device. The MOS device has a source, a drain, a drain insulation region adjacent to the drain, and a gate adjacent to the source. The resistor device is formed on the drain insulation region and is electrically connected to the drain. The resistor device has a plurality of resistor sections connected in series, and each of the plurality of resistor sections has a curved shape.