A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.

A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

A semiconductor device including an active region protruding from an upper surface of a substrate and extending in a first horizontal direction, at least two gate electrodes extending in a second horizontal direction and crossing the active region, the second horizontal direction crossing the first horizontal direction, a source/drain region in the active region between the gate electrodes may be provided. The source/drain region includes a recess region, an outer doped layer on an inner wall of the recess region, an intermediate doped layer on the outer doped layer, and an inner doped layer on the intermediate doped layer and filling the recess region. One of the outer doped layer or the intermediate doped layer includes antimony, and the inner doped layer includes phosphorous.

A method is provided for fabricating an LDMOS transistor. The method includes providing a base substrate. The method also includes forming a first well area doped with a first well ion in the base substrate. In addition, the method includes forming a second well area doped with a second well ion in the base substrate, where the second well area includes a first region adjacent to the first well area. Moreover, the method includes forming a first ion doping region doped with first ions in the first well area and the first region, where a type of the first ions is the same as a type of the first well ion and opposite to a type of the second well ion. Further, the method includes forming a gate structure on part of the first well area and part of the first region.

A semiconductor device includes a first semiconductor structure. The first semiconductor structure includes a first semiconductor material having a band-gap. The first semiconductor structure has a first surface. An insulating layer has first and second opposing surfaces. The first surface of the insulating layer is on the first surface of the first semiconductor structure. A second semiconductor structure is on the second surface of the insulating layer and includes a second semiconductor material having a band-gap that is smaller than the band-gap of the first semiconductor material. A floating electrode couples the first semiconductor structure to the second semiconductor structure.

An integrated circuit (IC) structure includes a first cell and a second cell abutting the first cell. The first cell includes a first fin-like field-effect transistor (FinFET). The first FinFET includes a first channel region in a first fin extending along a first direction, and a first gate electrode extending across the first channel region in the first fin along a second direction different from the first direction. The second FinFET includes a second channel region in a second fin aligned with the first fin along the first direction, and a second gate electrode extending across the second channel region in the second fin along the second direction. The second fin has a smaller width than the first fin.

An object of the present invention is to provide high-performance highly-reliable power semiconductor device.

The semiconductor device according to the present invention is provided with a semiconductor substrate of a first conductive type, a drain electrode formed on a back side of the semiconductor substrate, a drift layer of the first conductive type formed on a semiconductor substrate, a source area of the first conductive type, a current-diffused layer of the first conductive type electrically connected to the drift layer, a body layer of a second conductive type reverse to the first conductive type in contact with the source area and the current-diffused layer, a trench which pierces the source area, the body layer and the current-diffused layer, which is shallower than the body layer, and the bottom of which is in contact with the body layer, a gate insulating film formed on an inner wall of the trench, a gate electrode formed on the gate insulating film, and a gate insulating film protective layer formed between the current-diffused layer and the gate electrode.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening portion on each of opposing regions with the first region lying therebetween, and forming a high-concentration impurity region having a first conductivity type and being higher in impurity concentration than the silicon carbide layer in a region exposed through the first opening portion, by implanting ions into the main surface with the first mask layer being interposed are included.