Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.

A thin film transistor, a manufacturing method thereof, an array substrate and a display device are disclosed. The thin film transistor includes an active layer, as well as a source and a drain above the active layer, wherein the active layer includes a carrier trapping portion configured to trap photo-generated majority carriers.

An SOI semiconductor device includes a substrate, a buried oxide layer disposed on the substrate, a top semiconductor layer disposed on the buried oxide layer, a source doping region and a drain doping region in the top semiconductor layer, a channel region between the source doping region and the drain doping region in the top semiconductor layer, a gate electrode on the channel region, and an embedded doping region disposed in the top semiconductor layer and directly under the channel region. The embedded doping region acts as a hole sink to alleviate or avoid floating body effects.

Disclosed are an LTPS-based CMOS component and a method for manufacturing the same. The CMOS component includes an NMOS type LTPS. PN junctions are provided in an NMOS type LTPS channel to reduce the movement speed of electrons in the channel, so that hot electron effects can be avoided. The LTPS-based CMOS component can reduce the movement speed of electrons and avoid hot electron effects.

New device structure for single-legged Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI MOS) transistor is presented. This new structure imposes a hard barrier for an Impact-Ionizations current and for transients due to Single-Event-Effects (SEE's) in Body to laterally conduct (or diffuse) to the Source through the Body/Source junction. It forces these currents to conduct instead to the Source through an alternate path made of highly conductive Silicide. This alternate path effectively suppresses the latch-up of the built-in parasitic Bipolar structure without necessitating the incorporation of Body-Tied-Source (BTS) into the device layout which is known to increase the device periphery without correspondingly scaling its device current.

Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof, a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole, and a second main electrode provided on a second main surface of the semiconductor substrate.

In a manufacturing method for a semiconductor device formed over an SOI substrate, a first epitaxial layer is partially formed over an outer circumference end of a first semiconductor layer in a wide active region. Then, a second epitaxial layer is formed over each of the first semiconductor layers in a narrow active region and the wide active region. Thereby, a second semiconductor layer configured by a laminated body of the first semiconductor layer and the first and second epitaxial layers is formed in the wide active region and a third semiconductor layer configured by a laminated body of the first semiconductor layer and the second epitaxial layer is formed in the narrow active region.

Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof, a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole, and a second main electrode provided on a second main surface of the semiconductor substrate.

Manufacturing techniques and related semiconductor devices are disclosed in which the channel region of analog transistors and/or transistors operated at higher supply voltages may be formed on the basis of a very thin semiconductor layer in an SOI configuration by incorporating a counter-doped region into the channel region at the source side of the transistor. The counter-doped region may be inserted prior to forming the gate electrode structure. With this asymmetric dopant profile in the channel region, superior transistor performance may be obtained, thereby obtaining a performance gain for transistors formed on the basis of a thin semiconductor base material required for the formation of sophisticated fully depleted transistor elements.

The purpose of the invention is suppressing a kink phenomenon and improving the image quality of a display device. The display device has a TFT in a pixel. The TFT has a semiconductor layer, a first insulating layer under the semiconductor layer, a second insulating layer over the semiconductor layer, and a gate electrode facing the semiconductor layer with a gap. The gate electrode has a first gate electrode portion facing a lower surface of the semiconductor layer, a second gate electrode portion facing an upper surface of the semiconductor layer, and a third gate electrode portion facing a lateral surface of the semiconductor layer and connected to the first and second gate electrode portions. A laminated part where the first and second insulating layers are stacked is around the semiconductor layer, and a part of the laminated part is between the lateral surface and the third gate electrode portion.