A driving thin-film transistor can include a substrate; a first active layer disposed on the substrate and including a first protruding portion; a second active layer overlapping with the first active layer and including a second protruding portion; a gate electrode disposed between the first active layer and the second active layer; a source electrode connected to the first protruding portion of the first active layer; and a drain electrode connected to the second protruding portion of the second active layer, in which the first protruding portion of the first active layer and the second protruding portion of the second active layer are located at different positions.

New device structure for single-legged Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI MOS) transistor is presented. This new structure imposes a hard barrier for an Impact-Ionization current and for transients due to Single-Event-Effects (SEE's) in Body to laterally conduct (or diffuse) to the Source through the Body/Source junction. It forces these currents to conduct instead to the Source through an alternate path made of highly conductive Silicide. This alternate path effectively suppresses the latch-up of the built-in parasitic Bipolar structure without necessitating the incorporation of Body-Tied-Source (BTS) implant into the device structure that increases the total device periphery without correspondingly scaling its device current.

A circuit is formed on an SOI. The bias generator is connected to the gates of first and second transistors. In the bias generator, a first variable current source is connected to the power supply circuit via a power supply node. A third transistor is connected between the first variable current source and a ground-voltage source. A gate thereof is connected to the gate of the first transistor. A first operational amplifier controls a gate voltage of the third transistor so that a voltage at a second node between the first variable current source and the third transistor becomes almost equal to a reference-voltage. A first characteristics changer is connected to the gate of the third transistor or a second node, to change at least one loop gain characteristics and phase characteristics of a loop from the first operational amplifier, through the third transistor, to the first variable current source.

A thin film transistor includes a semiconductor layer, a gate, a source and a drain. The semiconductor layer includes a first heavily doped region, a second heavily doped region, a bridge region, a first channel region, a second channel region, a first lightly doped region and a second lightly doped region. The first lightly doped region connects the bridge region and the first channel region. The second lightly doped region connects the bridge region and the second channel region. The doping concentration of the bridge region is greater than that of the first lightly doped region and the second lightly doped region. The gate overlaps the bridge region, the first channel region, the second channel region, the first lightly doped region and the second lightly doped region. The source and the drain are electrically connected to the first heavily doped region and the second heavily doped region respectively.

A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

A device and structure for providing electrostatic discharge (ESD) protection. Schottky barrier diode (SBD) structure comprising a substrate of a first dopant polarity, a well region of a second dopant polarity formed on or within said substrate, an anode region of a first dopant polarity, a cathode of a second polarity, and a rectifying contact on said anode and/or said cathode, wherein said rectifying contact is formed substantially near the surface of said substrate to provide a rectifying barrier junction between the conducting layer and the semiconductor substrate, providing electrical coupling in said Schottky Barrier diode structure. The disclosure further includes SOI Schottky Barrier polysilicon-bound diodes (also known as Lubistor structures). Additionally, a diode configured SOI dynamic threshold MOSFET with rectifying barrier junctions on the drain or source region.

Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.

Disclosed are an LTPS-based COMS component and a method for manufacturing the same. The COMS component includes an NMOS type LTPS. PN junctions are provided in an NMOS type LTPS channel to reduce the movement speed of electrons in the channel, so that hot electron effects can be avoided. The LTPS-based CONN component can reduce the movement speed of electrons and avoid hot electron effects.

A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is T.sub.S1 and the thickness of the second region is T.sub.G1, T.sub.S1T.sub.G1.

In a manufacturing method for a semiconductor device formed over an SOI substrate, a first epitaxial layer is partially formed over an outer circumference end of a first semiconductor layer in a wide active region. Then, a second epitaxial layer is formed over each of the first semiconductor layers in a narrow active region and the wide active region. Thereby, a second semiconductor layer configured by a laminated body of the first semiconductor layer and the first and second epitaxial layers is formed in the wide active region and a third semiconductor layer configured by a laminated body of the first semiconductor layer and the second epitaxial layer is formed in the narrow active region.