A thin film transistor, an array substrate, a manufacturing method and a display device are provided. The thin film transistor includes a substrate and a gate layer, a source layer and a drain layer disposed on the substrate. The source layer and the drain layer are disposed in different layers and the drain layer and the gate layer are disposed in same and one layer.

A method for manufacturing an array substrate includes forming a buffer layer on a substrate; forming a source and a data line in the buffer layer, forming a first gate, a second gate, a first scan line, and a second scan line on the buffer layer, simultaneously; forming a semiconductor layer; forming a conductor layer by converting the semiconductor layer formed on the first scan line and the second scan line into a conductor; forming a first pixel electrode on the semiconductor layer and forming a second pixel electrode on the conductor layer, simultaneously.

In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.

A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer including an amorphous silicon, irradiating a region of the first silicon layer from a part or the whole of a predetermined region of the first silicon layer to an outside of the predetermined region with an energy beam so as to convert a portion of the first silicon layer into a polycrystalline silicon, a first etching step for etching the first silicon layer while leaving the predetermined region, forming a second silicon layer including an amorphous silicon so as to cover the predetermined region, a second etching step for etching the second silicon layer covering the predetermined region while leaving a part of the second silicon layer, the part larger than the predetermined region, and forming a source electrode and a drain electrode.

The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrode and the drain electrode.

A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer including an amorphous silicon, irradiating a region of the first silicon layer from a part or the whole of a predetermined region of the first silicon layer to an outside of the predetermined region with an energy beam so as to convert a portion of the first silicon layer into a polycrystalline silicon, a first etching step for etching the first silicon layer while leaving the predetermined region, forming a second silicon layer including an amorphous silicon so as to cover the predetermined region, a second etching step for etching the second silicon layer covering the predetermined region while leaving a part of the second silicon layer, the part larger than the predetermined region, and forming a source electrode and a drain electrode.

A display apparatus includes a pixel having a first area emitting light and a second area transmitting light. A pixel circuit unit is in the first area and includes a thin film transistor. An inorganic insulation layer is in the second area. A first insulation layer covers the pixel circuit unit in the first area, and has an opening exposing the inorganic insulation layer in the second area. A first electrode is on the first insulation layer in the first area. The first electrode is electrically connected to the pixel circuit unit. A second insulation layer covers edges of the first electrode and is outside the opening formed in the first insulation layer. A second electrode is in the first area. An intermediate layer, including an emissive layer, is between the first electrode and the second electrode.

According to one embodiment, a semiconductor device includes first to third semiconductor regions and first to third conductors. The second semiconductor region is separated from the first semiconductor region in a first direction. The third semiconductor region is provided between the first and the second semiconductor regions. The third conductor is separated from the third semiconductor region in a second direction intersecting the first direction. The third semiconductor region includes first and second partial regions. The first partial region includes a first metal element, and is amorphous. The second partial region is stacked with the first partial region in the second direction, and is polycrystalline. A first concentration of the first metal element in the first partial region is higher than a second concentration of the first metal element in the second partial region, or the second partial region does not include the first metal element.

In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.