In an embodiment a method for structuring a semiconductor surface includes providing the semiconductor surface, wherein the semiconductor surface is part of a GaN-semiconductor layer, irradiating the semiconductor surface with an electron beam in order to produce an irradiated section and anisotropic wet-chemical etching of the semiconductor surface, wherein an etching rate in the irradiated section is less than that in an unirradiated section of the semiconductor surface, and wherein no etching mask is applied to the semiconductor surface before anisotropic wet-chemical etching.

There is provided a structure manufacturing method, including: preparing an etching target with at least one surface comprising group III nitride; then in a state where the etching target is immersed in an etching solution containing peroxodisulfate ions; irradiating the surface of the etching target with light through the etching solution, and generating sulfate ion radicals from the peroxodisulfate ions and generating holes in the group III nitride, thereby etching the group III nitride, wherein in the etching of the group III nitride, the etching solution remains acidic during a period for etching the group III nitride by making the etching solution acidic at a start of etching the group III nitride, and the etching is performed, with a resist mask formed on the surface.

In an embodiment, a first recess and a second recess, designed to reach a first semiconductor layer, are formed in the portions of a first threading dislocation and a second threading dislocation having reached the surface. Further, the first semiconductor layer is oxidized through the first recess and the second recess to form an insulating film configured to cover the lower surface of a second semiconductor layer.

A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.

A method comprises providing a substrate comprising an n-type Al/In/GaN semiconductor material. A surface of the substrate is dry-etched to form a trench therein and cause dry-etch damage to remain on the surface. The surface of the substrate is immersed in an electrolyte solution and illuminated with above bandgap light having a wavelength that generates electron-hole pairs in the n-type Al/In/GaN semiconductor material, thereby photoelectrochemically etching the surface to remove at least a portion of the dry-etch damage.

In an embodiment, a first recess and a second recess, designed to reach a first semiconductor layer, are formed in the portions of a first threading dislocation and a second threading dislocation having reached the surface. Further, the first semiconductor layer is oxidized through the first recess and the second recess to form an insulating film configured to cover the lower surface of a second semiconductor layer.

The invention relates to a method for producing a back-contact solar cell (10), and to a back-contact solar cell (10) comprising a semiconductor substrate (12), in particular a silicon wafer, comprising a front side (16) and a back side (14), the solar cell (10) comprising electrodes (36) of a first polarity and electrodes (38) of a second polarity on the back side, characterized in that that the electrodes (36) of the first polarity are located on a highly doped silicon layer (20) of the first polarity, the highly doped silicon layer (20) being located on a first passivation layer (18) located on the semiconductor substrate, and the electrodes (38) of the second polarity directly electrically and mechanically contacting the semiconductor substrate (12) via highly doped base regions (30) of the second polarity of the semiconductor substrate (12).

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.