Embodiments of the disclosure provide a method for fabricating a lightly doped drain area, a thin film transistor, and a thin film transistor array substrate. In an embodiment of the disclosure, a poly-silicon layer, a gate insulation layer, and a gate metal layer are formed in sequence on a substrate; the gate metal layer is patterned to form a gate electrode; the gate insulation layer is etched to form a stepped structure, wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and the poly-silicon layer is doped by an ion doping process using the gate electrode and the gate insulation layer with the stepped structure as a mask to form both a lightly doped area and a heavily doped area.

An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.

A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.

An oxide semiconductor thin-film transistor device includes a gate electrode region, an oxide semiconductor region, a first source/drain electrode region, and a second source/drain electrode region. The oxide semiconductor region has a concentration distribution of an element capable of increasing resistance of an oxide semiconductor. The concentration distribution shows a first concentration at the centroid of a channel region overlapping the gate electrode region in a planar view. The concentration distribution shows a concentration higher than the first concentration in a vicinity of at least a part of a boundary defining an outer end of the channel region.

An LTPS pixel unit and a manufacturing method. The method includes following steps: forming a buffering layer on the substrate; forming a semiconductor pattern and a common electrode pattern which are disposed with an interval on the buffering layer; sequentially forming a first insulation layer, a gate electrode pattern and a second insulation layer on the semiconductor pattern; forming a source electrode pattern and a drain electrode pattern on the second insulation layer, wherein, the source electrode pattern and the drain electrode pattern electrically contact with the semiconductor pattern through a first contact hole at the first insulation layer and the second insulation layer; and forming a pixel electrode pattern on the second insulation layer, wherein, the pixel electrode pattern electrically contacts with the source electrode pattern or the drain electrode pattern. Accordingly, the present invention can save the cost and increase process yield.

A method for producing a microelectronic device with one or more transistor(s) including forming a first gate on a region of a semiconductor layer, forming a first cavity in the semiconductor layer, the first cavity having a wall contiguous with the given region, filling the first cavity in such a way as to form a first semiconductor block wherein a source or drain region of the first transistor is capable of being produced, by epitaxial growth of a first semiconductor material in the first cavity, the growth being carried out such that a first zone of predetermined thickness of the layer of first semiconductor material lines the wall contiguous with the given region, epitaxial growth of a second zone made of a second semiconductor material on the first zone.

A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.

Failure light emission of an EL element due to failure film formation of an organic EL material in an electrode hole 46 is improved. By forming the organic EL material after embedding an insulator in an electrode hole 46 on a pixel electrode and forming a protective portion 41b, failure film formation in the electrode hole 46 can be prevented. This can prevent concentration of electric current due to a short circuit between a cathode and an anode of the EL element, and can prevent failure light emission of an EL layer.

A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an inter-layer insulation film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.

An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.