A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.

A method and apparatus for reducing as-deposited and metastable defects relative to amorphous silicon (a-Si) thin films, its alloys and devices fabricated therefrom that include heating an earth shield positioned around a cathode in a parallel plate plasma chemical vapor deposition chamber to control a temperature of a showerhead in the deposition chamber in the range of 350° C. to 600° C. An anode in the deposition chamber is cooled to maintain a temperature in the range of 50° C. to 450° C. at the substrate that is positioned at the anode. In the apparatus, a heater is embedded within the earth shield and a cooling system is embedded within the anode.

A semiconductor device, the device including: a first single crystal substrate and plurality of logic circuits, where the first single crystal substrate has a device area, where the device area is significantly larger than a reticle size, where the plurality of logic circuits include an array of processors, where the plurality of logic circuits include a first logic circuit, a second logic circuit, and third logic circuit, where the plurality of logic circuits include switching circuits to support replacing the first logic circuit and the second logic circuit by the third logic circuit; and a built-in-test-circuit (“BIST”), where the built-in-test-circuit is connected to test at least the first logic circuit and the second logic circuit.

A thin film transistor is provided. The thin film transistor includes a base substrate; a first target layer on the base substrate; a first insulating layer on a side of the first target layer away from the base substrate; an intermediate layer on a side of the first insulating layer away from the first target layer; a second insulating layer on a side of the intermediate layer away from the first insulating layer; and a second target layer on a side of the second insulating layer away from the intermediate layer. The first target layer is electrically connected to the second target layer. The intermediate layer is one of a gate electrode and an active layer, and the first target layer and the second target layer together constitute another one of the gate electrode and the active layer.

The present disclosure discloses a temperature sensor, a display panel, and a display apparatus, in the field of sensors. The temperature sensor includes a ring oscillator consisting of n levels of phase inverters, where n is an odd number greater than or equal to 1. Each level of phase inverter includes a first thin film transistor (TFT) and a second TFT that are connected in series. An on/off state of the second TFT is configured to be in a normally-on state, an on/off state of the first TFT is configured to be determined by a signal input to the phase inverter, and mobility of an active layer material of the first TFT is greater than mobility of an active layer material of the second TFT.

A manufacturing method of a TFT substrate is a manufacturing method of a TFT substrate in which each of a source electrode and a drain electrode includes a lower source metal layer and an upper source metal layer. The manufacturing method of the TFT substrate includes the steps of: forming an upper source metal layer by etching an upper conductive film with the first resist layer as an etching mask; forming a lower source metal layer by etching a lower conductive film; removing the first resist layer and forming a second resist layer covering the upper source metal layer; and forming a source contact portion and a drain contact portion by etching a contact layer by dry etching with the second resist layer as an etching mask.

Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.

Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

A thin film transistor, a manufacturing method thereof, a display substrate, and a display device are provided. The thin film transistor includes: a substrate, an active layer, a gate, a source and a drain. The active layer is arranged on the substrate and formed as a grid, including silicon nanowires extending along a first direction, the active layer includes source and drain regions oppositely arranged along the first direction, and a channel region located therebetween. The gate is arranged on the substrate, and an orthographic projection of the gate onto the substrate overlaps with orthographic projections for silicon nanowires in the channel region onto the substrate. The source and drain are arranged on the substrate, the source contacts silicon nanowires in the source region, and the drain contacts silicon nanowires in the drain region.

A 3D semiconductor device including: a first single-crystal layer including a plurality of first transistors; at least one first metal layer disposed atop the plurality of first transistors; a second metal layer disposed atop the at least one first metal layer; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a plurality of fourth transistors disposed atop the plurality of third transistors; a third metal layer disposed atop the plurality of fourth transistors; a fourth metal layer disposed atop the third metal layer; a plurality of connecting metal paths from the fourth metal layer or the third metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error.