The present disclosure provides a thin-film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor of the present disclosure include a plurality of insulating layers, among which at least one insulating layer on the low temperature polysilicon layer comprises organic material, so vias could be formed in the organic material by an exposing and developing process, thereby effectively avoiding the over-etching problem of the low temperature polycrystalline silicon layer caused by dry etching process. By adopting the method for manufacturing the film transistors of the present disclosure, the contact area and uniformity of the drain electrode and the low temperature polysilicon material layer can be increased; the conductivity can be improved; and the production cycle of products can be greatly reduced and thereby improving the equipment capacity.

A light emitting display device includes a display panel including a light emitting area and a non-light emitting area; a phase delay layer disposed on the display panel; and a polarizer and an additional polarizer disposed on the phase delay layer. The display panel includes a transistor disposed on a substrate, an organic film overlapping the transistor and including an opening, a first electrode, an emission layer disposed on the first electrode and disposed corresponding to the light emitting area, and a second electrode disposed, the first electrode, the emission layer, and the second electrode form a light emitting diode (LED), the additional polarizer includes a polarization portion overlapping the opening of the organic film in a plan view and a non-polarization portion disposed in a region where the polarization portion is not disposed, and the polarization portion is disposed in a portion of the non-light emitting area.

Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region may be in the semiconductor substrate under the buried insulator layer. The at least one polycrystalline active region fill shape is laterally aligned over the polycrystalline isolation region, where provided. Where provided, the polycrystalline isolation region may extend to different depths in the semiconductor substrate.

A thin film transistor 101 includes: a gate electrode 2, a semiconductor layer 4 disposed on the gate electrode via a gate insulating layer 3, a source electrode 8s disposed on a portion of the semiconductor layer 4 via a first contact layer Cs, and a drain electrode 8d disposed on another portion via a second contact layer Cd. The first and second contact layers have a multilayer structure including N (where N is an integer equal to or greater than 1) two-layer structures S(n) (where n is an integer not smaller than 1 and not greater than N), each two-layer structure S(n) including a first amorphous silicon layer 71 that is directly in contact with the source or drain electrode, a second amorphous silicon layer 72(n), and a third amorphous silicon layer 73(n) that is directly in contact with an upper face thereof. In each two-layer structure S(n), n type impurity concentrations C2(n) and C3(n) of the second amorphous silicon layer and the third amorphous silicon layer and an n type impurity concentration C1 of the first amorphous silicon layer satisfy C2(n)<C3(n)<C1 for any given n.

The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

A manufacturing apparatus and a manufacturing method are provided. A manufacturing apparatus includes a chamber, and a stage disposed in the chamber. The stage includes an upper surface on which a target substrate is disposed, a lower surface opposite to the upper surface, a first side surface extending between the upper surface and the lower surface in a first direction, and a second side surface extending between the upper surface and the lower surface in a second direction perpendicular to the first direction. The first side surface is in a round shape, and at least a portion of the first side surface is convex toward an outside of the stage.

The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

A pixel includes: a driving transistor including a gate electrode coupled to a first node, a first electrode coupled to a second node, and a second electrode coupled to a third node; a first initialization transistor coupled between the first node and a first initialization voltage line, and including a gate electrode coupled to a scan line, where the first initialization voltage line is configured to supply a first initialization voltage; a first emission control transistor coupled between a fourth node and a fifth node and including a gate electrode coupled to the first node; a second emission control transistor coupled between the third node and the fifth node and including a gate electrode coupled to an emission control line; and a light-emitting element coupled between the fourth node and a driving low voltage line. The driving transistor and the first emission control transistor are different types of transistors.

A semiconductor device includes a conductive line that extends in a first direction on a substrate, a first oxide semiconductor layer, including a first crystalline oxide semiconductor material containing a first metal element, on the conductive line, a second oxide semiconductor layer, which is in physical contact with the first oxide semiconductor layer and is connected to the conductive line, on the conductive line, a gate electrode that extends in a second direction, which crosses the first direction, on a side of the second oxide semiconductor layer, and a capacitor structure connected to the second oxide semiconductor layer on the second oxide semiconductor layer and the gate electrode, wherein the second oxide semiconductor layer includes a second crystalline oxide semiconductor material containing the first metal element and second and third metal elements, which are different from the first metal element.