A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f)selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

A display device includes a pixel circuit and a light-emitting element, the pixel circuit including: a transistor with a first structure including a crystalline silicon semiconductor film and a first gate electrode; and a transistor with a second structure including an oxide semiconductor film and a second gate electrode, the display device further includes: a first interlayer insulation film; and a second interlayer insulation film, wherein the pixel circuit includes: a drive transistor that has the first structure: and a capacitive element, the capacitive element includes: a first capacitor electrode electrically connected to a first gate electrode of the drive transistor; a second capacitor electrode opposite the first capacitor electrode; and a dielectric film between the first capacitor electrode and the second capacitor electrode, and the dielectric film is disposed in a different layer than are the first interlayer insulation film and the second interlayer insulation film.

Disclosed is a display panel including: a substrate divided into a first area and a second area positioned outside the first area; a buffer layer disposed in the first area and the second area and disposed on the substrate; a first thin-film transistor including a polycrystalline semiconductor layer disposed in the first area and disposed on the buffer layer, and a first gate electrode disposed on the polycrystalline semiconductor layer; a second thin-film transistor including an oxide semiconductor layer disposed in the first area and disposed on the buffer layer, and a second gate electrode disposed on the oxide semiconductor layer; a first intermediate insulating layer disposed between the first area and the second area and interposed between the first thin-film transistor and the second thin-film transistor; a first contact hole passing through the first intermediate insulating layer on the polycrystalline semiconductor layer; and a second contact hole passing through the first intermediate insulating layer in the second area.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a vertical stack of semiconductor channels, a source on a first side of the vertical stack of semiconductor channels, and a drain on a second side of the vertical stack of semiconductor channels, In an embodiment, a metal is below the source and in direct contact with the source, where a centerline of the metal is substantially aligned with a centerline of the source.

An organic light emitting display (OLED) device includes an organic light emitting diode having an anode and a cathode. The organic light emitting diode is configured to receive a reference voltage. A control transistor includes a first control electrode and a first semiconductor active layer. The control transistor is configured to receive a control signal. A driving transistor includes a second control electrode that is electrically connected to the control transistor, an input electrode that is configured to receive a power voltage, an output electrode that is electrically connected to the anode of the organic light emitting diode, and a second semiconductor active layer that includes a different material from that of the first semiconductor active layer. A shielding electrode is disposed on the second semiconductor active layer, overlapping the driving transistor, and configured to receive the power voltage.

The present disclosure relates to a pixel displaying an image. A pixel includes an organic light emitting diode, a first transistor controlling an amount of current flowing from a first driving power supply to a second driving power supply via the organic light emitting diode in response to a voltage of a first node; a storage capacitor connected between the first node and the first driving power supply; a second transistor connected between a data line and the first node and turned on when a scan signal is supplied to a first scan line, and an auxiliary transistor connected between the second transistor and the data line and turned on when a scan signal is supplied to a second scan line. The second transistor and the auxiliary transistor have an overlapping turn-on period, and the second transistor is turned off before the auxiliary transistor is turned off.

A display includes a substrate having a driver circuit with hybrid devices. The driver circuit includes first to fourth transistors. The first transistor includes a first control end connected to a clock signal, a first end connected to a high voltage, and a second end connected to a first node. The second transistor comprises metal oxide semiconductor, and includes a second control end connected to an input signal, a third end connected to a second node, and a fourth end connected to the first node. The third transistor comprises polysilicon semiconductor, and includes a third control end connected to the first node, and a fifth end connected to the high voltage, and a sixth end connected to an output voltage. The fourth transistor includes a fourth control end connected to the input signal, a seventh end connected to the third node, and an eighth end connected to the output voltage.

Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.