A leadframe includes a first conductive layer, a plurality of conductive pillars and a first package body. The first conductive layer has a first surface and a second surface opposite to the first surface. The plurality of conductive pillars are disposed on the first surface of the first conductive layer. The first package body is disposed on the first surface of the first conductive layer and covers the conductive pillars. The conductive pillars and the first conductive layer are integratedly formed.

A method of making a micro-module structure comprises providing a substrate, the substrate having a substrate surface and comprising a substrate post protruding from the substrate surface. A component is disposed on the substrate post, the component having a component top side and a component bottom side opposite the component top side, the component bottom side disposed on the substrate post. The component extends over at least one edge of the substrate post. One or more component electrodes are disposed on the component.

A display device includes: a substrate including a display area having a plurality of pixels, a pad area having a plurality of pads, and a non-display area including a fan-out area between the display area and the pad area; at least one first fan-out line in the fan-out area; at least one second fan-out line in the fan-out area and electrically disconnected from the first fan-out line; first, second, and third insulating layers sequentially arranged on the substrate; and a first conductive layer between the substrate and the first insulating layer, a second conductive layer on the second insulating layer, and a third conductive layer on the third insulating layer, wherein each of the first and second fan-out lines has a multi-layered stacking structure in which a first sub-line, a second sub-line, and a third sub-line provided in different layers are stacked.

An electronic package having a miniaturized footprint and a method for manufacturing the same is provided. Due to the arrangement of bottom contacts of the electronic package using a first partial vias, a footprint is obtained that is miniaturized with respect to the known electronic package comprising a same-sized electronic component. The electronic package according to the present disclosure enables packaging multiple electronic components while nevertheless minimally increasing the footprint with respect to conventional electronic packages.

A power semiconductor module includes a semiconductor board and a number of semiconductor chips attached to the semiconductor board. Each semiconductor chip has two power electrodes. An adapter board is attached to the semiconductor board above the semiconductor chips. The adapter board includes a terminal area for each semiconductor chip on a side facing away from the semiconductor board. The adapter board, in each terminal area, provides a power terminal for each power electrode of the semiconductor chip associated with the terminal area. Each power terminal is electrically connected via a respective vertical post below the terminal area with a respective semiconductor chip and each of the power terminals has at least two plug connectors. Jumper connectors interconnect the plug connectors for electrically connecting power electrodes of different semiconductor chips.

A power module (2) including a rigid insulated substrate (10) mounted on a baseplate (4) is disclosed. An additional circuit carrier (6, 8) is mounted on the baseplate (4) adjacent to the rigid insulated substrate (10). The additional circuit carrier (6, 8) has a rigidity which is less than that of the rigid insulated substrate (10).

A semiconductor package includes a redistribution substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip mounted on the first surface of the redistribution substrate, an under bump interconnection layer on the second surface of the redistribution substrate, an electronic device mounted on the under bump interconnection layer, and a solder bump disposed on the under bump interconnection layer and horizontally spaced apart from the electronic device. The under bump interconnection layer includes conductive patterns respectively connected to the electronic device and the solder bump, and a passivation layer covering the conductive patterns. The passivation layer includes a plurality of trenches disposed between the electronic device and the solder bump.

A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.

A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.