The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

A semiconductor device includes an insulated circuit board in which a metal layer is formed on one surface of an insulating board and a semiconductor element having a polygonal shape when viewed in a plan view that is bonded to the metal layer via a bonding material. The metal layer of the insulated circuit board has a recess that exposes the insulating board at a position corresponding to at least one corner of the semiconductor element.

The present disclosure provides a method of transferring an electronic element using a stamping and magnetic field alignment technology and an electronic device including an electronic element transferred using the method. In the present disclosure, a polymer may be simultaneously coated on a plurality of electronic elements using the stamping process, and the polymer may be actively coated on the electronic elements without restrictions on process parameters such as size and spacing of the electronic elements. Moreover, the self-aligned ferromagnetic particles have an anisotropic current flow through which current flows only in the aligned direction. Therefore, the current may flow only vertically between the electronic element and the electrode, and there is no electrical short circuit between a peripheral LED element and the electrode.

A double sided cooling module that includes a leadframe with a top Direct Copper Bonded (DCB) substrate and two or more power transistor submodules. Each one of the power transistor submodules includes a bottom DCB substrate, a spaced-apart row of first wires attached to a top metal layer of the bottom DCB substrate proximate to the first side of the top metal layer, a semiconductor die having a bottom side load path contact attached to a top surface of a die pad portion of the top metal layer, a top side control contact electrically coupled via at least one bond wire to a top surface of a control pad portion of the top metal layer, and an electrically conductive and thermally conductive spacer that is attached to the top side load path contact and to a bottom metal layer of the top DCB substrate. At least one of the first wires is attached to the control pad portion of the top metal layer and to a bottom metal layer of the top DCB substrate. Other ones of the first wires are attached to the die pad portion of the top metal layer and to the bottom metal layer of the top DCB substrate.

A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.

The invention relates to a method for manufacturing a power electronic module (1) by additive manufacturing, characterized in that it comprises the steps of: making or fixing preforms (15) of polymer material on at least one face of an insulating substrate (2a) covered with at least one layer of metal (2b, 2c), referred to as a metallized substrate (2), depositing a first metal layer (17) on the preform (15), depositing by electroforming a second metal layer (18) on the first metal layer (17).

A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); a predetermined signal line (w1) arranged in the wiring layer of the quantum chip (111); first shield wires (ws1) arranged in the wiring layer of the quantum chip (111) along the predetermined signal line (w1); a second shield wire (ws2) arranged in the wiring layer of the interposer (112); and a second connection part (150) that is provided between the interposer (112) and the quantum chip (111) so as to contact the first shield wires (ws1) and the second shield wire (ws2).

An electronic device includes a support substrate. A face is covered with a soldermask layer. At least part of the soldermask layer includes roughnesses providing a rough grip surface. An electronic die is mounted on the support substrate. A molding resin encapsulates the electronic die and partially or completely covers the soldermask layer.

A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.

The invention relates to display device and method of manufacturing the same. The display device includes: a substrate; a driving pad disposed on the substrate; an insulating layer exposing the driving pad and disposed on the substrate; a circuit board including a circuit pad overlapping the driving pad; and a connector disposed between the circuit board and the insulating layer and including a plurality of conductive particles electrically connecting the driving pad and the circuit pad, the driving pad including: a first pad disposed on the substrate; and a second pad disposed on the first pad and having an opening exposing the first pad.