A thin film transistor includes a base substrate and an active layer on the base substrate. The active layer includes a source electrode contact part, a drain electrode contact part, and a channel part between the source electrode contact part and the drain electrode contact part. The source electrode contact part and the drain electrode contact part are lightly doped parts. The source electrode contact part includes a first barrier part. The drain electrode contact part includes a second barrier part. Each of the first barrier part and the second barrier part includes a semiconductor material having an acceptor defect or an acceptor-like defect. Each of the source electrode contact part and the drain electrode contact part includes a semiconductor material having a donor defect or a donor-like defect. The first barrier part and the second barrier part are respectively on two sides of the channel part.

A semiconductor device with high on-state current is provided. The semiconductor device includes a first oxide; a second oxide over the first oxide; a third oxide over the second oxide; a first insulator over the third oxide; a conductor over the first insulator; a second insulator that is in contact with a part of a top surface of the second oxide, a part of a side surface of the second oxide, and a part of a side surface of the third oxide; a third insulator that is in contact with a top surface of the second insulator and the other side surface of the third oxide; a fourth insulator over the third insulator; and a fifth insulator that is in contact with a top surface of the third oxide, a top surface of the first insulator, a top surface of the conductor, and a top surface of the third insulator, where the second oxide includes a first region, a second region, a third region, a fourth region positioned between the first region and the third region, and a fifth region positioned between the second region and the third region, where the conductor is provided above the third region to overlap with the third region, and where the second insulator is in contact with the first region and the second region.

A thin film transistor (10) may include a substrate (100); a buffer layer (300) on a surface of the substrate (100); an active layer (400) on a surface of the buffer layer (300) opposite from the substrate (100); a gate insulating layer (500) on a surface of the active layer (400) opposite from the substrate (100), and a gate (600) on a surface of the gate insulating layer (500) opposite from the substrate (100). A width of the active layer (400) may be smaller than a width of the gate (600), and an orthographic projection of the gate (600) on the substrate (100) may cover an orthographic projection of the active layer (400) on the substrate (100).

A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the base substrate includes a semiconductor body that can be doped, and a first conductive layer and a second conductive layer that are on the semiconductor body; the first transistor includes a first doped region in contact with the first electrode of the first transistor, and a second doped region in contact with a second electrode of the first transistor, and the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have a same doping type, and are both in the semiconductor body.

The present disclosure provides a thin film transistor, a manufacturing method thereof, and a display device, and the thin film transistor of the present disclosure includes: a substrate; a gate, a gate insulating layer, an active layer, a source and drain layer sequentially provided on the substrate, and the source and drain layer is correspondingly provided at a first source contact region and a first drain contact region of the active layer. A planarization layer is provided between the gate insulating layer and the substrate, the planarization layer is in a same layer as the gate and in direct contact with the gate, and an upper surface of the planarization layer is flush with an upper surface of the gate.

A semiconductor device with high on-state current is provided.

The semiconductor device includes a first oxide; a second oxide over the first oxide; a third oxide over the second oxide; a first insulator over the third oxide; a conductor over the first insulator; a second insulator that is in contact with a part of a top surface of the second oxide, a part of a side surface of the second oxide, and a part of a side surface of the third oxide; a third insulator that is in contact with a top surface of the second insulator and the other side surface of the third oxide; a fourth insulator over the third insulator; and a fifth insulator that is in contact with a top surface of the third oxide, a top surface of the first insulator, a top surface of the conductor, and a top surface of the third insulator, where the second oxide includes a first region, a second region, a third region, a fourth region positioned between the first region and the third region, and a fifth region positioned between the second region and the third region, where the conductor is provided above the third region to overlap with the third region, and where the second insulator is in contact with the first region and the second region.

A thin film transistor, a method for fabricating the same, an array substrate, a display panel, and a display device are provided. The thin film transistor includes a substrate, and an active layer on the substrate, wherein the active layer includes a poly-silicon layer and has a channel region and two electrode connection regions respectively on two sides of the channel region, and the channel region includes a plurality of lightly drain doping segments, which are spaced apart along from one of the electrode connection regions to the other electrode connection region, and channel segments located between the lightly drain doping segments.

A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.

A thin film transistor includes an active layer including a channel portion; a gate electrode spaced apart from the active layer and overlapping at least a part of the active layer; and source and drain electrodes connected with the active layer and spaced apart from each other, wherein the channel portion includes, a first boundary portion connected with one of the source and drain electrodes; a second boundary portion connected with the other one of the source and drain electrodes; and a main channel portion interposed between the first boundary portion and the second boundary portion, and wherein at least a part of the second boundary portion has a thickness smaller than a thickness of the main channel portion.

A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.