A thin-film transistor substrate includes a semiconductor layer disposed on a substrate, a gate insulating layer disposed on the semiconductor layer, a first electrode that at least partly overlaps the semiconductor layer, wherein the gate insulating layer is disposed between the first electrode and the semiconductor layer, a plurality of thin-film layers disposed on the first electrode, and a second electrode that at least partly overlaps the first electrode, wherein the plurality of thin-film layers are disposed between the second electrode and the first electrode, wherein at least one of the plurality of thin-film layers includes amorphous silicon.

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

A display device that is suitable for increasing its size is provided. The display device includes first to third wirings, a first transistor, first to third conductive layers, and a first pixel electrode; the first wiring extends in a first direction and intersects with the second and the third wirings; the second and the third wirings each extend in a second direction intersecting with the first direction; a gate of the first transistor is electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring through the first to the third conductive layers; the second conductive layer includes a region overlapping with the third wiring; the first conductive layer, the third conductive layer, and the first pixel electrode contain the same material; the first wiring and the second conductive layer contain the same material; the first wiring is supplied with a selection signal; and the second and the third wirings are supplied with different signals.

Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.

A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

In various embodiments, electronic devices such as touch-panel displays incorporate interconnects featuring a conductor layer and, disposed above the conductor layer, a capping layer comprising an alloy of Cu and one or more refractory metal elements selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni.

The present disclosure discloses a memory cell and a memory device including the same. The memory cell includes a thin film transistor layer, a gate conductive layer, a first heater, a second heater, a phase change layer, and a dielectric layer. The thin film transistor layer includes a channel layer and a first source/drain structure and a second source/drain structure in contact with opposite sides of the channel layer. The gate conductive layer is disposed beneath the gate dielectric layer to control turn-on or turn-off of the channel layer. The first and second heaters are respectively disposed over the first and second source/drain structures. The phase change layer is disposed over the channel layer and in contact with the first and second heaters. The dielectric layer is disposed beneath the phase change layer, and the phase change layer is separated from the channel layer by the dielectric layer.

This organic-EL display apparatus comprises an organic-EL display panel including: a substrate that is provided with pixel drive circuits to drive respective pixels arranged in a matrix along each of a first direction and a second direction, and organic light-emitting elements being provided to each of the pixels and connected to any one of the pixel drive circuits. The organic-EL display panel comprises a signal output circuit to supply a signal to each of the pixel drive circuits arranged in a line along the first direction or the second direction. The signal output circuit includes thin film transistors and is formed around a display region on a surface of the substrate. The thin film transistors include a semiconductor layer including a region to be a channel between a source electrode and a drain electrode. The semiconductor layer is formed of amorphous silicon.

A display device includes a substrate, an electrostatic protecting component and a shielding layer. The substrate has a display region and a peripheral region located outside the display region. The electrostatic protecting component is disposed on the substrate in the peripheral region, and the electrostatic protecting component includes a semiconductor layer. The shielding layer is disposed on the substrate in the peripheral region, wherein the shielding layer overlaps the semiconductor layer.