A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is lower in crystallinity than the first region and the second region.

An array substrate, a method of manufacturing thereof, and a display panel are provided. In the array substrate, a lesser thickness of an active layer in a GOA area achieves improved response time of thin film transistor in the GOA area, and a greater thickness of the active layer in a display area reduces diffusion of photons in the active layer, so as to decrease an influence of negative bias of thin film transistor in the display area. Additionally, different demands for characteristics of the array substrate in the display area and in the GOA area may be met, such that quality of the display panel may be improved.

A light emitting diode display device includes a substrate, a first layer disposed on the substrate, a first transistor disposed on the first layer and including a first gate electrode, and a light emitting diode connected to the first transistor, wherein the first layer may overlap the first gate electrode, and may include a first region including a first material and a second region including a second material different from the first material, the first material may include amorphous silicon doped with impurities, and the second material may include amorphous silicon.

The present disclosure relates to a method for manufacturing a panel, including the following steps: providing a substrate; forming a first transparent conductive layer on the substrate; treating the first transparent conductive layer with a plasma including a gas with low reducing ability; forming a first insulating layer with a via hole on the first transparent conductive layer; and forming a second transparent conductive layer on the first insulating layer, wherein the method further comprises a step of forming a transistor on the substrate after the step of forming the first transparent conductive layer on the substrate, and the transistor is electrically connected to the first transparent conductive layer through the via hole; and a transparency of the panel is greater than or equal to 90% and less than 100%. The present disclosure further provides a panel manufactured by the aforesaid method of the present disclosure.

A display device includes a driver circuit monolithically integrated in a display panel. The display panel has a plurality of pixel units and signal lines; and a driver circuit including a first circuit element and a second circuit element integrally formed on the display panel and electrically connected to each other, wherein patterning density of the first circuit element and patterning density of the second circuit element would be substantially different from each other if the first and second circuit elements were laid out as concentrated individual circuit elements, but where the driver layout includes at least two spaced apart first circuit element regions over which the first circuit element is distributively formed and the driver layout includes an interposed second circuit element region in which at least part of the second circuit element is formed.

A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

A display device includes an array substrate, a second substrate and a black matrix. The array substrate includes a first substrate, at least one electrostatic protecting component and a shielding layer. The first substrate has a display region and a peripheral region located outside the display region. The electrostatic protecting component is disposed on the first substrate in the peripheral region, and the electrostatic protecting component includes a semiconductor layer. The shielding layer includes an insulating material, and the shielding layer is disposed on the first substrate in the peripheral region, wherein the shielding layer overlaps the semiconductor layer. The second substrate is opposite to the first substrate. The black matrix is disposed between the second substrate and the first substrate. The shielding layer is disposed between the black matrix and the first substrate.

The manufacturing method for TFT array substrate of the invention exposes the negative photoresist material on the passivation layer with a semi-transmissive mask to form a crosslinked portion, first and second uncrosslinked portion; then, performs the first development to remove the first uncrosslinked portion and forms a via on the passivation layer, performs the ashing treatment for thinning the negative photoresist material to expose the second uncrosslinked portion, performs the second development to remove the second uncrosslinked portion; deposits transparent conductive material on negative photoresist material and exposed passivation layer to form a pixel electrode on passivation layer, and finally removes the remaining negative photoresist material and the transparent conductive material with photoresist stripping solution. The invention, using step-wise development, solves the technical difficulty of forming a halftone structure with a negative photoresist material, and enables feasibility of the use of the negative photoresist material in the 3mask process.

An array substrate includes: a substrate; a black light-shading layer disposed on the substrate; a first metal layer correspondingly disposed on the black light-shading layer and thereby the black light-shading layer being located between the substrate and the first metal layer; an active material layer disposed on the first metal layer; a second metal layer disposed on the active material layer; a passivation layer disposed on the second metal layer and with a contact hole; a color filter layer disposed on the passivation layer; and a pixel electrode layer disposed on the color filter layer and connected to the second metal layer through the contact hole. Moreover, a liquid crystal display panel and a manufacturing method of an array substrate also are provided.

A thin film transistor according to one embodiment comprises a gate electrode; a semiconductor layer being formed using amorphous silicon and comprising a region overlapping with the gate electrode; a gate insulating layer; and a source electrode and a drain electrode facing each other with a predetermined interval therebetween. The gate electrode comprises a first layer having a first work function; and a second layer having a second work function and being interposed between the first layer and the gate insulating layer. The semiconductor layer comprises an intrinsic region being formed with non-doped amorphous silicon; and a low concentration impurities region. The second work function is less than the first work function when n-type impurities are contained in the low concentration impurities region, while the second work function is greater than the first work function when p-type impurities are contained in the low concentration impurities region.