A method for manufacturing the array substrate includes: forming a gate metal layer on a base by a first patterning process and forming a gate insulating layer on the gate metal layer; forming a semiconductor layer and a source/drain metal layer by a second patterning process on the resulted base, the source/drain metal layer including a data line and a metal electrode connected to the data line; forming a first electrode on the resulted base and forming a channel region by a third patterning process, the channel region causing the metal electrode to form a source electrode and a drain electrode; forming a passivation layer and an organic insulating layer by a fourth patterning process on the resulted base; the organic insulating layer at least corresponding to the data line; and forming a second electrode by a fifth patterning process on the resulted base.

A method of manufacturing array substrate and a display panel, wherein, the method of manufacturing array substrate includes: depositing a gate electrode, a gate insulation layer, a semiconductor layer, a metal layer and a photoresist; forming an non-exposure area, a partial exposure area and a full exposure area through exposure and developing; then, performing a first ashing treatment and a wet etching to form a metal layer recess, and performing a second ashing treatment to etch off residual photoresist which remains in the metal layer recess after the first ashing treatment; and finally performing a dry etching to form a pattern of a channel region.

There is provided a manufacture method of an array substrate of a display device using TFT as a pixel control unit, an array substrate, and a display apparatus. In this method, when a data line and source and drain electrodes of a TFT are prepared, a half-tone mask is used to retain at least one part of a photoresist on the data line; and the retained photoresist is softened by heating so that the at least one part of the data line is coated by the retained photoresist.

The present application discloses a thin film transistor. The thin film transistor includes a base substrate; an active layer; an etch stop layer on a side of the active layer distal to the base substrate; and a source electrode and a drain electrode on a side of the etch stop layer distal to the active layer. The active layer includes a channel region, a source electrode contact region, and a drain electrode contact region. An orthographic projection of the etch stop layer on the base substrate surrounds an orthographic projection of the drain electrode contact region on the base substrate. An orthographic projection of the source electrode contact region on the base substrate at least partially peripherally surrounding the orthographic projection of the etch stop layer on the base substrate.

The present application discloses a photodiode structure including multiple light trapping elements. Each light trapping element includes an N-type silicon layer with a recessed structure therein, an intrinsic silicon layer disposed overlying the N-type silicon layer including a side region and a bottom region inside the recessed structure, and a P-type silicon layer disposed as an inner layer overlying the intrinsic silicon layer inside the recessed structure. A radial PIN junction is formed around a nominal axis of the recessed structure.

The present disclosure relates to a conductive layer, a thin film transistor and manufacturing methods therefor, an array substrate and a display device, in the field of displays. The conductive layer comprises: a metal layer and an organophosphorus-metal complex covering the metal layer. In the embodiments of the present disclosure, the organophosphorus-metal complex is manufactured on the surface of the metal layer to form the conductive layer. The conductive layer is adopted as an electrode material. In one aspect, the organophosphorus-metal complex has conductivity and can prevent the surface of metal from making contact with oxygen, thereby avoiding metal oxidation under the premise of not affecting the performances of the electrode when serving as a material of the electrode in a TFT. In the other aspect, the organophosphorus-metal complex can increase a binding force between the metal and photoresist and avoids stripping of the photoresist. Therefore, etching liquid is prevented from etching the metal in a position without the need of etching. The conductive layer provided by the present disclosure has the performances in the above two aspects. Therefore, the stability and electronic transmission performances of the electrode can be improved by adopting such a conductive layer to manufacture the electrode of the thin film transistor.

Certain aspects of the present disclosure provide a variable transistor-based capacitive element implemented on a glass or dielectric substrate. Such a variable transistor-based capacitive element may be suitable for use as a tunable capacitor in a passive-on-glass (POG) device, for example. One example device having a tunable capacitance generally includes a glass or dielectric substrate and a transistor disposed above the glass or dielectric substrate. The transistor has a gate region, a drain region, and a source region, wherein a capacitance of the transistor is configured to vary based on a voltage between the gate region and the drain region.

An array substrate and a display device are provided. The array substrate comprises a substrate, a switch assembly, a metal lines, a pixel electrode and a plurality of pixel units. The switch assembly is disposed on the substrate, and the switch assembly comprises a plurality of transistors. The pixel electrode comprises a plurality of line-shaped branches. The branches comprises a horizontal branch and a vertical branch perpendicular to each other, and a drain line of one of the transistors is disposed under one of the horizontal branchs closest to the transistor. Each pixel unit comprises a plurality of display domains, and the display domains of each of the pixel units are symmetrical with respect to the horizontal branch or the vertical branch. A projection of the metal lines on the array substrate overlaps with a vertical projection of the horizontal or vertical branch on the array substrate.

Disclosed are a thin film transistor, a method for fabricating the same, an array substrate, and a display device. The method of this disclosure includes: fabricating an anti-etching layer pattern on an active layer, wherein the anti-etching layer pattern is doped with an electrically conductive medium; etching away an area of the active layer, which is not covered with the anti-etching layer pattern, to form an active layer pattern, and reserving the anti-etching layer pattern; and fabricating a source and a drain of the thin film transistor.

A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3). The content ratio differentiation between the first and the third sub-layers (105-1, 105-3) affects a lateral etch profile associated with a gap (106) generated in the second conductive layer (105) between the source and the drain electrodes (105a, 105b), where the associated gap (106) width in the third sub-layer (105-3) is wider than that in the first sub-layer (105-1).