Disclosed is an array substrate, a display panel, and a display device. The array substrate includes: a substrate (100), a plurality of pixel units (110) disposed on a side of the base substrate (100), a chip (200) configured for providing signal to the pixel units (110), signal lines (120) corresponding to each of pixel units (110), and via holes (130) penetrating the base substrate (100). By disposing the chip (200) on the side of the base substrate (100) opposed to the pixel units (110) and electrically connecting the pixel units (110) to the chip (200) through the signal lines (120) in the via holes (130), the frame portion which is used for accommodating the chip could be omitted and a real frameless design is achieved.

A film patterning method is provided. The method comprises: performing a dry etching process on a film to be patterned, so as to form a patterned film; removing a suspended particle on the patterned film; and performing another dry etching process on the patterned film after the suspended particle is removed, to form a final pattern of the film. By moving or completely removing the suspended particle on the patterned film and then performing another dry etching process on the patterned film to etch away the etching residue, existence of the etching residue is completely avoided in the final pattern of the film, so that the product yield is improved and the product quality is ensured.

A display device includes: a substrate; a first thin film transistor unit disposed on the substrate and comprising a first active layer comprising a silicon layer, wherein the first active layer comprises a channel region, a source region and a drain region; a second thin film transistor unit disposed on the substrate and comprising a second active layer comprising a metal oxide layer; and a display medium disposed on the first thin film transistor unit and the second thin film transistor unit. Herein, a thickness of the silicon layer in the channel region is less than or equal to a thickness of the silicon layer in the source region.

[Summary] [Problem] A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. [Solving Means] By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized.

The present invention provides an amorphous silicon thin film transistor and a manufacturing method of the amorphous silicon thin film transistor, which comprise: a substrate, a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, an N+-doped layer, a protective insulating layer, and a passivation layer. The N+-doped layer is disposed between the active layer and the source/drain electrode layer. The protective insulating layer is disposed on the source/drain electrode layer. A channel is formed in the source/drain electrode layer and penetrates the N+-doped layer and the protective insulating layer. The passivation layer covers the channel and the protective insulating layer. The protective insulating layer and the source/drain electrode layer are flush with each other in the channel.

An organic light-emitting display apparatus includes a substrate, an active layer of a thin film transistor formed over the substrate, a gate insulating layer formed over the active layer, a gate electrode of the thin film transistor formed over the gate insulating layer, an interlayer insulating layer formed over the gate electrode and the first electrode, a source electrode and a drain electrode formed over the interlayer insulating layer, a pixel electrode including a first region in direct contact with an upper surface of the interlayer insulating layer and a second region in direct contact with an upper surface of one of the source electrode and the drain electrode, a pixel defining layer covering the source and drain electrodes and including an opening which exposes the first region of the pixel electrode in an area that does not overlap the thin film transistor.

The present invention includes: a multilayer film forming step of forming a multilayer film constituted by a plurality of metal films layered together; after the multilayer film forming step, a resist forming step of forming a resist film having patterned openings on the multilayer film; after the resist forming step, a dry etching step of dry etching the multilayer film to remove at least one metal film located at the top of the multilayer film and exposed by the openings; after the dry etching step, a wet etching step of wet etching the multilayer film to remove at least the metal films exposed by the openings.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A display panel and manufacturing method thereof, and a display device and health monitoring method thereof. The display panel includes a base substrate and a sonic sensor disposed on the base substrate. The sonic sensor is configured to monitor a sonic wave.

The present application discloses a thin film transistor. The thin film transistor includes a base substrate; an active layer; an etch stop layer on a side of the active layer distal to the base substrate; and a source electrode and a drain electrode on a side of the etch stop layer distal to the active layer. The active layer includes a channel region, a source electrode contact region, and a drain electrode contact region. An orthographic projection of the etch stop layer on the base substrate surrounds an orthographic projection of the drain electrode contact region on the base substrate. An orthographic projection of the source electrode contact region on the base substrate at least partially peripherally surrounding the orthographic projection of the etch stop layer on the base substrate.