A display device including: a first substrate including a first base substrate and a lower pad disposed on one end of the first base substrate on a side; a second substrate disposed above the first substrate and including a second base substrate and an upper pad disposed on an end of the second base substrate on the side; a side pad electrically connected to the lower pad and the upper pad; and a sealing member disposed between the first substrate and the second substrate. The sealing member includes an insulating resin and conductive balls dispersed in the insulating resin, and the upper pad and the lower pad are electrically connected to each other through the conductive balls.

A pixel includes an organic light-emitting diode; a first transistor that receives a signal in response to a voltage applied to a first node and controls an amount of current flowing from a second node electrically connected to a power supply voltage line to the organic light-emitting diode; a fourth transistor electrically connected between the first node and a first initializing voltage line; and a bias capacitor electrically connected between the second node and a light-emission control line, the bias capacitor including a first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the bias capacitor and a semiconductor layer of the first transistor are disposed on a same layer, and the second capacitor electrode of the bias capacitor and a second portion included in a gate electrode of the fourth transistor are disposed on a same layer.

Provided is a thin film transistor array substrate. The thin film transistor array substrate includes a first sub-pixel region and a second sub-pixel region; a first thin film transistor and a second thin film transistor disposed in the first sub-pixel region and the second sub-pixel region on the substrate, respectively; and a first insulating layer including at least one first dummy hole formed above or adjacent to the first thin film transistor, and a plurality of second dummy holes formed in a greater number than the at least one first dummy hole, formed above or adjacent to the second thin film transistor.

Embodiments of the disclosure provide a method for fabricating a lightly doped drain area, a thin film transistor, and a thin film transistor array substrate. In an embodiment of the disclosure, a poly-silicon layer, a gate insulation layer, and a gate metal layer are formed in sequence on a substrate; the gate metal layer is patterned to form a gate electrode; the gate insulation layer is etched to form a stepped structure, wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and the poly-silicon layer is doped by an ion doping process using the gate electrode and the gate insulation layer with the stepped structure as a mask to form both a lightly doped area and a heavily doped area.

A semiconductor device includes a base substrate, a first transistor disposed on the base substrate, the first transistor including a first input electrode, a first output electrode, a first control electrode, and a first semiconductor pattern including a crystalline semiconductor, a second transistor disposed on the base substrate, the second transistor including a second input electrode, a second output electrode, a second control electrode, and a second semiconductor pattern including an oxide semiconductor, a plurality of insulating layers disposed on the base substrate, and an upper electrode disposed on the first control electrode with at least one insulating layer of the plurality of insulating layers interposed between the upper electrode and the first control electrode. The upper electrode overlaps the first control electrode and forms a capacitor with the first control electrode.

A thin film transistor (TFT) structure is provided herein, which comprises a substrate, a light-shielding resin, a polysilicon, a gate electrode insulator, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode. The light-shielding resin has functions of light-shielding and insulation. With doping through two through holes at two sides, the manufacturing process is simplified, the exposure process is simplified, the production time is shortened, the usage of masks is decreased, and the production cost is lowered.

An array substrate and a method of manufacturing the same are provided. The array substrate includes a substrate, a plurality of thin film transistors disposed on the substrate, and a planarization layer covering the plurality of thin film transistors and filled a region defined by the plurality of thin film transistors and the substrate.

A display device including a substrate, a gate driver disposed on the substrate and including a plurality of stages, a clock signal line disposed on the substrate, and transmitting a clock signal to at least one of the stages, a transistor disposed on the substrate, and a light blocking layer disposed between the substrate and the transistor and overlapping the transistor. The clock signal line includes a first conductive line and a second conductive line overlapping the first conductive line, and the first conductive line is disposed in the same layer as the light blocking layer.

A display device includes a base substrate including a first substrate and a second substrate sequentially laminated, a lower semiconductor layer disposed on at least one of the first substrate and the second substrate, a buffer layer disposed on the base substrate, an active semiconductor layer disposed on the buffer layer and including a first active layer of a first transistor and a second active layer of a second transistor, a first insulating layer disposed on the active semiconductor layer, and a first conductive layer disposed on the first insulating layer and including a first gate electrode of the first transistor and a second gate electrode of the second transistor, wherein the lower semiconductor layer overlaps the first active layer, and does not overlap the second active layer.

An LTPS pixel unit and a manufacturing method. The method includes following steps: forming a buffering layer on the substrate; forming a semiconductor pattern and a common electrode pattern which are disposed with an interval on the buffering layer; sequentially forming a first insulation layer, a gate electrode pattern and a second insulation layer on the semiconductor pattern; forming a source electrode pattern and a drain electrode pattern on the second insulation layer, wherein, the source electrode pattern and the drain electrode pattern electrically contact with the semiconductor pattern through a first contact hole at the first insulation layer and the second insulation layer; and forming a pixel electrode pattern on the second insulation layer, wherein, the pixel electrode pattern electrically contacts with the source electrode pattern or the drain electrode pattern. Accordingly, the present invention can save the cost and increase process yield.