Provided is a thin film transistor array substrate having at least one thin film transistor. The thin film transistor includes a semiconductor layer having a channel area with a first doping concentration on a substrate, a source-drain area disposed at opposite sides of the channel area and with a second doping concentration greater than the first doping concentration, and a substantially undoped area extending from the source-drain area. The substrate has a gate insulating layer on the semiconductor layer and a gate electrode disposed on the gate insulating layer and overlapping the channel area in at least some portions. The substrate has a source electrode and a drain electrode, each insulated from the gate electrode and electrically connected to the source-drain area. The gate electrode includes a first gate electrode layer and a second gate electrode layer, wherein the second gate electrode layer is thicker than the first gate electrode layer.

A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.

Provided are an array substrate and a liquid crystal display device. The array substrate includes a base plate and a low temperature poly-silicon layer, a first insulation layer, a gate zone, a second insulation layer, a source zone, a drain zone, a planarization layer, a first transparent conductive layer, a third insulation layer, and a second transparent conductive layer that are arranged on the same side of the base plate. The gate zone covers the first insulation layer. The source zone and the drain zone are respectively connected to two ends of the low temperature poly-silicon layer. The second transparent conductive layer is connected to the drain zone and the second transparent conductive layer includes a plurality of spaced conductive zones.

A liquid crystal display panel and a mobile phone. The liquid crystal display panel includes a first screen and a second screen which are disposed adjacently, the two screens are controlled by independent light strips, the light strips are both disposed in a backlight module, wherein, the second screen includes an array substrate and a color filter substrate, the array substrate includes multiple reflective electrodes disposed separately. Accordingly, the second screen of the liquid crystal panel of the present invention can reflect an external environment light to decrease the dependence on the backlight source such that the power consumption can be saved.

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between a metal electrode layer and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a metal electrode layer disposed on a barrier layer formed above a gate insulating material layer, an interface layer disposed on the metal electrode layer, wherein the interface layer is an oxygen free dielectric material layer sized to be formed predominately on the metal electrode layer, and an insulating material layer disposed on the interface layer, wherein the insulating material layer is an oxygen containing dielectric layer.

A potential of a gate of a driving transistor is fixed, and the driving transistor is operated in a saturation region, so that a current is supplied thereto anytime. A current control transistor operating in a linear region is disposed serially with the driving transistor, and a video signal for transmitting a signal of emission or non-emission of the pixel is input to a gate of the current control transistor via a switching transistor.

A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.

A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern. The pre protection layer has a material with a first etch selectivity that is different from a second etch selectivity of the second insulation layer with respect to the etching gas.

The present invention provides a thin film transistor array substrate and a liquid crystal display panel. The thin film transistor array substrate comprises: a substrate; a light shielding layer, located at a middle part on a surface of the substrate; a buffer layer, covering the light shielding layer; a Low Temperature Poly-silicon layer, being located on the buffer layer, and corresponding to the light shielding layer; an isolation layer, covering the Low Temperature Poly-silicon layer, and the isolation layer comprises a through hole, wherein a width of the through hole is smaller than a width of the light shielding layer; a metal layer, located on the isolation layer, and the metal layer is connected with the Low Temperature Poly-silicon layer via the through hole. The thin film transistor array substrate and the liquid crystal display panel have a higher aperture ratio.

The present application provides a low temperature poly-silicon thin film, a low temperature poly-silicon thin film transistor and manufacturing methods thereof, and a display device. The manufacturing method of a low temperature poly-silicon thin film comprises steps of: forming an amorphous silicon thin film on a base; and performing a laser annealing process on the amorphous silicon thin film by using a mask plate to form a low temperature poly-silicon thin film, wherein the mask plate includes a transmissive region and a shielding region surrounding the transmissive region, and two sides of the shielding region adjacent to the transmissive region are in concave-convex shapes. Performance of the low temperature poly-silicon thin film formed by the manufacturing method of a low temperature poly-silicon thin film in the present application is enhanced.