A manufacturing method of an array substrate, an array substrate and a display device are disclosed. The manufacturing method of the array substrate includes: providing a base substrate (200); forming a semiconductor layer on the base substrate; depositing an etch stop layer material on the semiconductor layer; subjecting the etch stop layer material to a wet etching process to form an etch stop layer; subjecting the semiconductor layer to a dry etching process to form an active layer, wherein the active layer includes a first region and a second region surrounding the first region, an orthographic projection of the etch stop layer on the base substrate completely coincides with an orthographic projection of the first region of the active layer on the base substrate.

A display device includes an array substrate, a second substrate and a black matrix. The array substrate includes a first substrate, at least one electrostatic protecting component and a shielding layer. The first substrate has a display region and a peripheral region located outside the display region. The electrostatic protecting component is disposed on the first substrate in the peripheral region, and the electrostatic protecting component includes a semiconductor layer. The shielding layer includes an insulating material, and the shielding layer is disposed on the first substrate in the peripheral region, wherein the shielding layer overlaps the semiconductor layer. The second substrate is opposite to the first substrate. The black matrix is disposed between the second substrate and the first substrate. The shielding layer is disposed between the black matrix and the first substrate.

A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

Disclosed are a low-temperature polycrystalline silicon thin film transistor (LTPS TFT), a method for fabricating the same, an array substrate, a display panel, and a display device. The LTPS TFT includes an active layer, a source, a drain, a gate, and a gate insulating layer which are arranged on a substrate. The gate insulating layer is arranged between the active layer and the gate, and a graphene oxide layer which is arranged between the active layer and the gate insulating layer. Since the graphene oxide layer is arranged between the active layer and the gate insulating layer, the interface between the active layer and the gate insulating layer of polycrystalline (P-Si) has a reduced roughness and interfacial defect density, and a pre-cleaning process is not necessary for the gate insulating layer.

A method of forming fine patterns includes the steps of forming a conductive layer on a base part, forming a sacrificial layer including an adhesive material on the conductive layer, the adhesive material including a catechol group, forming resist patterns on the sacrificial layer, and forming fine patterns by patterning the conductive layer using the resist patterns as a mask.

There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.

An array substrate, a method for fabricating the array substrate and a display device are described. The array substrate includes: a first gate electrode metal layer; a first gate insulation layer; an active layer on the first gate insulation layer; an etching barrier layer on the active layer; a source-drain metal layer including a source electrode and a drain electrode that contact with two sides of the active layer respectively; a second gate insulation layer on the source-drain metal layer; and a second gate electrode metal layer on the second gate insulation layer. The array substrate has an optimized TFT performance and a reduced gate line resistance, and light may be blocked from irradiating on the active layer, which is beneficial to restrain IR Drop, drifting of TFT threshold voltages or generation of a light-incurred leakage current on the active layer. Performance of the display device is improved.

This disclosure provides a communication device and a manufacturing method thereof. The manufacturing method of the communication device includes the following steps: providing a first dielectric layer, wherein the first dielectric layer includes a first region and a second region, and the first dielectric layer has a first surface and a second surface opposite to the first surface; providing a second dielectric layer; combining the first dielectric layer and the second dielectric layer with a sealing element, so that the sealing element is disposed between the first surface of the first dielectric layer and a third surface of the second dielectric layer; after combining the first dielectric layer and the second dielectric layer, thinning the second surface of the first dielectric layer; and disposing a first communication element on the first surface of the first dielectric layer in the first region.

The present application relates to a display panel, a display screen and a display terminal. The display panel comprises a substrate provided with pixel circuits thereon; a pixel-defining layer; a light-emitting structure layer; a first electrode layer disposed on the pixel circuits and comprising a plurality of first electrodes; a second electrode disposed on the light emitting structure layer and being a surface electrode; and a scanning line and a data line both connected to each of the pixel circuits; wherein, sub-pixels in adjacent sub-pixel rows are staggered with one another and/or sub-pixels in adjacent sub-pixel columns are staggered with one another; the scanning line supplies a voltage to the pixel circuit to control turning-on and turning-off of the pixel circuit, and when the pixel circuit is turned on, a drive current from the data line is directly supplied to the first electrode to control light-emitting of the corresponding sub-pixel.