An organic light-emitting display apparatus includes a substrate, an active layer of a thin film transistor formed over the substrate, a gate insulating layer formed over the active layer, a gate electrode of the thin film transistor formed over the gate insulating layer, an interlayer insulating layer formed over the gate electrode and the first electrode, a source electrode and a drain electrode formed over the interlayer insulating layer, a pixel electrode including a first region in direct contact with an upper surface of the interlayer insulating layer and a second region in direct contact with an upper surface of one of the source electrode and the drain electrode, a pixel defining layer covering the source and drain electrodes and including an opening which exposes the first region of the pixel electrode in an area that does not overlap the thin film transistor.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A display panel and manufacturing method thereof, and a display device and health monitoring method thereof. The display panel includes a base substrate and a sonic sensor disposed on the base substrate. The sonic sensor is configured to monitor a sonic wave.

The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other. The passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein. The first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.

The present application discloses a thin film transistor. The thin film transistor includes a base substrate; an active layer; an etch stop layer on a side of the active layer distal to the base substrate; and a source electrode and a drain electrode on a side of the etch stop layer distal to the active layer. The active layer includes a channel region, a source electrode contact region, and a drain electrode contact region. An orthographic projection of the etch stop layer on the base substrate surrounds an orthographic projection of the drain electrode contact region on the base substrate. An orthographic projection of the source electrode contact region on the base substrate at least partially peripherally surrounding the orthographic projection of the etch stop layer on the base substrate.

A thin film transistor includes a substrate, and a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode which are on the substrate. The active layer includes a channel region between the source electrode and the drain electrode and the channel region includes an edge region along a channel length direction and a main region outside the edge region. The thin film transistor further includes an auxiliary layer, a projection of the auxiliary layer on the substrate is at least partially overlapped with a projection of the edge region of the channel region on the substrate, and the auxiliary layer is configured to enhance a turn-on voltage of the edge region of the channel region.

The present invention provides a thin film transistor array substrate and a liquid crystal display panel. The thin film transistor array substrate comprises: a substrate; a light shielding layer, located at a middle part on a surface of the substrate; a buffer layer, covering the light shielding layer; a Low Temperature Poly-silicon layer, being located on the buffer layer, and corresponding to the light shielding layer; an isolation layer, covering the Low Temperature Poly-silicon layer, and the isolation layer comprises a through hole, wherein a width of the through hole is smaller than a width of the light shielding layer; a metal layer, located on the isolation layer, and the metal layer is connected with the Low Temperature Poly-silicon layer via the through hole. The thin film transistor array substrate and the liquid crystal display panel have a higher aperture ratio.

The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.

An array substrate, manufacturing method thereof, and display device. The array substrate comprises a subpixel unit, and the subpixel unit comprises: a first transparent common electrode; a pixel electrode disposed over and insulated from the first transparent common electrode, wherein an orthographic projection of the first transparent common electrode on a surface where the pixel electrode is located has an overlapping portion with the pixel electrode; and a second transparent common electrode disposed over and insulated from the pixel electrode.

According to one embodiment, a thin-film transistor includes a polycrystalline semiconductor layer, a gate electrode opposing the polycrystalline semiconductor layer, a gate insulating film provided between the gate electrode and the polycrystalline semiconductor layer and in contact with the gate electrode, and an amorphous layer provided between the gate insulating film and the polycrystalline semiconductor layer, and in contact with the gate insulating film and the polycrystalline semiconductor layer.