Discussed is a method of manufacturing a LCD device, the method including: forming a gate in each of a plurality of pixel areas on a substrate; forming a gate insulator to cover the gate; forming a semiconductor layer on the gate insulator, and forming a photoresist (PR) on the semiconductor layer; doping high-concentration impurities at the semiconductor layer by using the photoresist (PR) as a mask to form an active layer, a source, and a drain; and doping low-concentration impurities at the semiconductor layer by using the photoresist (PR) as the mask to form a lightly doped drain (LDD) between the active layer and the source and between the active layer and the drain.

A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

A high electron mobility transistor (HEMT) includes a substrate comprising a first surface and a second surface on opposing sides of the substrate, a channel layer on the first surface of the substrate opposite the substrate, a barrier layer on the channel layer, a source contact comprising a first ohmic contact on an upper surface of the barrier layer, and a via extending from the second surface of the substrate to the first ohmic contact.

A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.

An electroluminescent display device and a fabricating method thereof are provided. The device has a TFT layer, a first functional layer, an electroluminescent layer, a second functional layer, and a functional bar disposed sequentially. The device uses Seebeck effect of constituent material of p-type Bi.sub.2Te.sub.3 of the functional bar to absorb heat of the TFT layer for converting the heat into electric energy, thereby effectively reducing heat of the TFT layer, reducing aging of circuit and organic material, and improving life of the electroluminescent display device. A work function of p-type Bi.sub.2Te.sub.3 material of the functional bar is 5.3 eV. An electroluminescent material has a HOMO energy level ranging from 5 to 6 eV. Under a driving of a thermoelectromotive force, majority carriers (holes) in the constituent material of p-type Bi.sub.2Te.sub.3, are injected into the electroluminescent layer to improve a carrier concentration therein, thereby improving emission luminance of the electroluminescent display device.

A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.

An AlGaN/GaN HEMT based on fluorinated graphene passivation and a manufacturing method thereof. Monolayer graphene (108) is transferred to an AlGaN (104) surface, is treated by using fluoride ions and then is insulated to thereby replace a conventional nitride passivation layer. Then, a high-k material (109) is grown on the graphene (108), and the high-k material (109) and the graphene (108) are jointly used as a gate dielectric for preparing an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene (108) has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. The structure and the method are simple, the effect is remarkable and the application prospect in technical fields of microelectronics and solid-state electronics is wide.

An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.

A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.