B81C1/00253

SENSOR AND METHOD FOR REDUCING AN INTERFERENCE SIGNAL COMPONENT IN A MEASURING SIGNAL FROM A SENSOR
20220381583 · 2022-12-01 ·

A sensor including a sensor element for acquiring a measuring signal, the measuring signal including at least one useful signal component in a useful signal frequency range and at least one interference signal component in an interference signal frequency range, and a readout circuit for converting the measuring signal into an analog electrical sensor signal. A feedback circuit is provided, which feeds back the output signal of the readout circuit to the input of the readout circuit at which the measuring signal is applied, and the total transmission function H(s) of the readout circuit and feedback circuit induces an attenuation of the analog sensor signal in the interference signal frequency range, while the analog sensor signal in the useful signal frequency range is not attenuated.

Micromechanical component having a diaphragm

Measures are described with the aid of which not only a rupture, but also cracks may be detected in the diaphragm structure of a micromechanical component with the aid of circuit means integrated into the diaphragm structure. At least some circuit elements are integrated for this purpose into the bottom side of the diaphragm, i.e., into a diaphragm area directly adjoining the cavern below the diaphragm.

SEMICONDUCTOR STRUCTURES

The present application relates to structures for supporting mechanical, electrical and/or electromechanical components, devices and/or systems and to methods of fabricating such structures. The application describes a primary die comprising an aperture extending through the die. The aperture is suitable for receiving a secondary die. A secondary die may be provided within the aperture of the primary die.

WAFER LEVEL STACKED STRUCTURES HAVING INTEGRATED PASSIVE FEATURES

A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

Wafer level stacked structures having integrated passive features

A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

METHOD FOR MANUFACTURING A MEMS DEVICE BY FIRST HYBRID BONDING A CMOS WAFER TO A MEMS WAFER

A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

Semiconductor structures
11736866 · 2023-08-22 · ·

The present application relates to structures for supporting mechanical, electrical and/or electromechanical components, devices and/or systems and to methods of fabricating such structures. The application describes a primary die comprising an aperture extending through the die. The aperture is suitable for receiving a secondary die. A secondary die may be provided within the aperture of the primary die.

Semiconductor structures
11223907 · 2022-01-11 · ·

The present application relates to structures for supporting mechanical, electrical and/or electromechanical components, devices and/or systems and to methods of fabricating such structures. The application describes a primary die comprising an aperture extending through the die. The aperture is suitable for receiving a secondary die. A secondary die may be provided within the aperture of the primary die.

Composite structures
11814284 · 2023-11-14 · ·

The application relates to structures, e.g. substrates for supporting semiconductor die. The substrate defines a frame which lateral surrounds one or more die and is provided in contact with at least one side surface of the die, wherein the frame defines upper and lower surfaces of the substrate.

Wafer level shim processing

An integrated circuit assembly including a first wafer bonded to a second wafer with an oxide layer, wherein a first surface of the first wafer is bonded to a first surface of the second wafer. The assembly can include a bonding oxide on a second surface of the second wafer, wherein a surface of the bonding oxide is polished. The assembly can further include a shim secured to the bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly.