Patent classifications
G01R31/2633
SYSTEM AND METHOD FOR IDENTIFYING NON-SWITCHING SEMICONDUCTOR SWITCHES
The invention relates to a system (30) and a method for identifying a non-switching semiconductor switch (34a, 36a). The system (30) comprises a first semiconductor switch (34a), a first semiconductor component (34b), a second semiconductor switch (36a), a second semiconductor component (36b), a first resistor (64b), a second resistor (66b) and a detection unit (38). The detection unit (38) is designed to identify, on the basis of a curve of a first voltage dropping across the first resistor (64b), whether the first semiconductor switch (34a) is not switching. The detection unit (38) is designed to identify, on the basis of a curve of a second voltage dropping across the second resistor (66b), whether the second semiconductor switch (36a) is not switching.
DIODE VOLTAGE MEASUREMENT SYSTEMS
A diode voltage measurement system can include a plurality of diodes connected in series along a single line. The plurality of diodes can include N diodes. The system can include a plurality of capacitors for at least N−1 of the diodes. Each capacitor can be connected in parallel to the single line with a respective diode to form a respective diode-capacitor (DC) pair. Each DC pair can be configured such that each DC pair reaches a steady state voltage at a different time. The system can include a current supply connected to the single line to supply a current to the line. The system can include a control module configured to sense a total voltage across the single line and to successively determine voltage of each diode from the total voltage based on the current, a known total steady state voltage, and known time-to-steady-state-voltages of each DC pair and/or diode.
SWITCHING AMPLIFIER AND METHOD FOR ESTIMATING REMAINING LIFETIME OF A SWITCHING AMPLIFIER
A switching amplifier includes a power device and a processing device. The power device is configured for powering a load and is comprised of a plurality of switches. The processing device configured to calculate a switch junction temperature for a bonding wire in each switch based at least in part on a power loss of each switch; generate a first accumulated fatigue damage of the bonding wire in each switch based on the switch junction temperature; and generate an estimated remaining lifetime of the switching amplifier based on the first accumulated fatigue damages of the bonding wires in each switch.
Transient voltage suppressor bit stimulation
A transient voltage suppressor (TVS) can include an input line, a return line, and a plurality of TVS diodes disposed in series between the input line and the return line. The TVS can include a switch assembly operatively connected to the plurality of TVS diodes and configured to bypass at least one of the plurality of TVS diodes to allow a remainder of the plurality of TVS diodes to be tested at a voltage that is lower than if the switch assembly were not employed.
SOLID-STATE POWER SWITCH PROGNOSTICS
Systems, methods, techniques and apparatuses of prognostic testing are disclosed. One exemplary embodiment is a power switch system comprising a power switch; a current sensor; a test current injection circuit comprising: a first direct current (DC) bus rail including an output terminal and a first power supply terminal, a second DC bus rail including an input terminal and a second power supply terminal, a diode coupled to the first DC bus rail, and a leg coupled to the first DC bus rail between the diode and the first power supply terminal and coupled to the second DC bus rail between the input terminal and the second power supply terminal, the leg including a capacitor and a semiconductor device coupled in series; and a controller configured to operate the test current injection circuit to transmit a test current to the current sensor and receive a voltage based on the test current.
Electronic test equipment apparatus and methods of operating thereof
An electronic test equipment apparatus includes a power terminal configured to receive power, an interface for a device under test (DUT), at least one power transistor connected in series between the power terminal and the interface for the DUT, and a protection circuit. The protection circuit is configured to: switch on the at least one power transistor, to electrically connect the power terminal to the DUT through the interface as part of a test routine; and subsequently automatically switch off the at least one power transistor after a predetermined delay, to electrically disconnect the power terminal from the DUT regardless of whether the DUT passes or fails the test routine. A voltage clamp circuit for electronic test equipment and corresponding methods of testing devices using such electronic test equipment are also described.
Device and method for testing semiconductor devices
A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.
Fault recognition
A fault identification apparatus includes a detector and a plug interface connected with the detector, where the plug interface includes a first measuring terminal and a second measuring terminal; when fault identification is performed for a PSU in a communication apparatus under test, the first measuring terminal is connected with a first end of the PSU, and the second measuring terminal is connected with a second end of the PSU; and the detector obtains a voltage value between the first measuring terminal and the second measuring terminal to determines whether a failure occurs to the PSU based on the voltage value.
FAULT RECOGNITION
A fault identification apparatus includes a detector and a plug interface connected with the detector, where the plug interface includes a first measuring terminal and a second measuring terminal; when fault identification is performed for a PSU in a communication apparatus under test, the first measuring terminal is connected with a first end of the PSU, and the second measuring terminal is connected with a second end of the PSU; and the detector obtains a voltage value between the first measuring terminal and the second measuring terminal to determines whether a failure occurs to the PSU based on the voltage value.
FLEXIBLE WIDE BANDGAP DOUBLE PULSE TESTING METHODOLOGY
A test and measurement instrument has a user interface, one or more probes to allow the instrument to connect to a device under test (DUT), and one or more processors configured to execute code to cause the one or more processors to: receive one or more user inputs through the user interface, at least one of the user inputs to identify at least one analysis to be performed on the DUT, receive waveform data from the DUT when the DUT is activated by application of power from a power supply, and application of one of a first and second pulse or multiple pulses from a source instrument, perform the at least one analysis on the waveform data, and display the waveform data and analysis on the user interface. A method of automatically performing a double pulse test and analysis on a device under test (DUT) includes receiving a user input through a user interface on a test and measurement instrument, the user input to identify at least one analysis to be performed on waveform data received from the DUT, receiving the waveform data from the DUT when the DUT is activated by application of power from a power supply, and application of one of a first and a second pulse or multiple pulses from a source instrument, performing the analysis on the waveform data, and displaying the waveform data and analysis on the user interface.