Embodiments of the present disclosure provide sensors inside an In-Circuit Tester (ICT) that measure stress on a Printed Circuit Board (PCB) every time the ICT runs through a manufacturing process. This ICT can comprise an Internet of Things (IoT) device which can measure, monitor, record, and show stress data that is being exerted by ICTs on the mounted PCB in real-time during tests thereby providing technicians an ability to oversee failures based on historical data that the IoT device provides.

An apparatus and a method for inspecting a semiconductor includes a water tank which includes a housing, an interior of which is filled with a liquid, and a support block which provides a settling surface for an inspection object inside the housing. A plurality of signal generators are installed on a bottom surface of the housing, and output a frequency signal in a direction in which the inspection object is located. A power supply operates the signal generators. A probe is placed above the inspection object, and a receiver which operates with the probe and is attached to a bottom surface of the support block. Foreign matter remaining on the inspection object are removed, using a plurality of frequency signals which are output by the plurality of signal generating units.

A burn-in board management system includes a production burn-in apparatus and a burn-in board status computer. The production burn-in apparatus is configured to test a plurality of integrated circuit devices mounted in slots of a burn-in board and comprising a first controller configured to generate a first burn-in board status map, wherein the first controller is further configured to suspend the burn-in board when the first burn-in board status map of the burn-in board demonstrates that more than a threshold percentage of the slots of the burn-in board are determined to be malfunctioned. The burn-in board status computer is communicably connected with the first controller of the production burn-in apparatus and configured to receive the first burn-in board status map.

A testing apparatus for testing electrical components and/or conductor track structures. The testing apparatus includes: a multiplicity of testing locations, each receiving an electrical component and/or a conductor track structure; a selection device for selecting one of the testing locations; electrical lines disposed in rows and electrical lines disposed in columns for the supply of an alternating voltage to the component or structure, situated at the selected testing location; Z diodes for the electrical connection of the respective component and/or structure at the respective testing location via one of the Z diodes to one of the rows of electrical lines; a signal generator developed to generate a test signal that has a voltage signal as the sum of a square wave signal and a wave-shaped signal; and an electromigration device for applying a direct voltage signal to the components and/or structures to bring about electromigration in the components and/or structures.

A method for dynamic intelligent testing of a target, to be tested according to projects, includes calling up a data distribution model of a project in response to a target being tested by the project, and obtaining a test range corresponding to the project based on the data distribution model. The method further includes obtaining a test value when the target is at a minimum power consumption value by testing the target based on the test range, and updating the data distribution model and the test range of the project based on the test value.

The present invention relates to a method for diagnosing the state of the capacitor in a modular converter. The method for diagnosing the state of the capacitor in a modular converter includes determining a FIT table depending on the input voltage and temperature of an internal capacitor for multiple sample modular converters; detecting, by an input voltage detection unit, the input voltage of the capacitor in a target modular converter, the state of the capacitor of which is to be diagnosed, during a preset period; detecting, by a temperature detection unit, the temperature of the capacitor of the target modular converter during the preset period; calculating the cumulative mean for the input voltage and the temperature, which are respectively detected by the input voltage detection unit and the temperature detection unit during the preset period; and selecting, by a control unit, a FIT value corresponding to the cumulative mean of the input voltage and the temperature, from the FIT table; and extracting the MTBF of the capacitor from the FIT table.

The present disclosure relates to a method for estimating parameters of a junction of a power semi-conductor element comprising: •—Detecting at least one stable on-line operating condition through measurements (2, 3, 4) of Von, Ion, Tc on a semi-conductor module (1) where Ion is a current for which the on-state voltage Von of the semi-conductor is sensitive to the temperature and Tc is the temperature of the casing of said semi-conductor element; •—Measuring and storing at least one parameter set Von, Ion, Tc of said at least one stable operating condition; •—in a calculating unit (52), providing calculations for minimizing the error between a junction temperature estimation Tj of an electrical model Tj=F(Von, Ion, θelec) comprising a first set of unknown parameters θelec and another junction temperature estimation Tjmod of a loss/thermal model Tj=G(lon, Tc, θ mod) comprising a second set of unknown parameters θ mod and obtaining at least one set of parameters θelec and at least one parameter θ mod providing minimization of said error; •—providing the calculated value of Tj with at least one of the calculated parameters sets θelec and/or θ mod and the measured Von, Ion, Tc; •—Storing the at least one parameters set θelec and/or θ mod and/or Tj.

An electronic load testing system is configured to emulate aspects of an integrated circuit (IC). A control module of the system is configured to be electrically coupled to a first location on a printed circuit board (PCB) of an electronic assembly, and a load module is configured to be electrically coupled to a second location on the PCB. The load module includes a load cell configured to selectively conduct current from a power supply of the electronic assembly. The first location and the second location are spaced apart and in electronic communication via one or more traces of the PCB. The control module is configured to communicate with the load module via the one or more traces of the PCB. In some examples, the load module and the IC have an equivalent form factor, such that the load module can be installed in place of the IC.

A burn-in board management system includes a production burn-in apparatus and a burn-in board status computer. The production burn-in apparatus is configured to test a plurality of integrated circuit devices mounted in slots of a burn-in board and comprising a first controller configured to generate a first burn-in board status map, wherein the first controller is further configured to suspend the burn-in board when the first burn-in board status map of the burn-in board demonstrates that more than a threshold percentage of the slots of the burn-in board are determined to be malfunctioned. The burn-in board status computer is communicably connected with the first controller of the production burn-in apparatus and configured to receive the first burn-in board status map.

Techniques are described for systematically and efficiently converting or otherwise accelerating latent defects in semiconductor devices into gross defects by applying appropriate defect acceleration stimulus to the semiconductor devices. Techniques are also described for evaluating test patterns to determine their effectiveness in accelerating the transition of latent defects to gross defects. This evaluation effectively allows various stress patterns to be graded or ranked, so that an optimal or high-confidence one can be selected. Such grading of possible stress patterns increases the probability that a given latent defect will escalate or otherwise manifest.