The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly. The robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck.

A semiconductor package test system includes a test pack on which a semiconductor package is loaded, and a semiconductor package testing apparatus. The semiconductor package testing apparatus includes a receiving section that receives the test pack. The receiving section includes a pack receiving slot into which the test pack is inserted. The test pack includes a chuck on which the semiconductor package is fixed, a probe block disposed above the chuck, and a connection terminal. The receiving section includes a receiving terminal that is electrically connected to the connection terminal when the receiving terminal contacts the connection terminal. The probe block includes at least one needle configured to be electrically connected to the semiconductor package disposed on the chuck upon the chuck moving toward the semiconductor package. The receiving section is provided in plural.

A chip detection device, a chip detection system and a control method. The chip detection device includes a support plate (100), a probe holder (110) disposed on an upper part of the support plate (100), a detection platform, and a first driving device (120) connected to the probe holder (110). The chip detection system includes a cabinet (600), which is internally provided with a chip detection device, a controller, a loading manipulator (910), an unloading manipulator (920), a chip tray bracket (700) disposed on a side of the loading manipulator (910), and a distribution tray (800) disposed on a side of the unloading manipulator (920). According to the chip detection device, the chip detection system and the control method, during the rotation of the turntable (200), the filling, detection and classification of the chips are all controlled to be automatically completed under the control of an automatic control program, which greatly improves the efficiency of the chip detection.

The present invention is directed to a system for testing printed circuit boards. The system is configured to test the simultaneously test a multiplicity of printed circuit boards. The system examines the electrical characteristics of a printed circuit board and is operable to identify if a printed circuit board meets a desired characteristic.

A testing apparatus for Data Storage Devices (DSDs) includes a chassis and at least one interface module configured to be removably inserted into the chassis and house a plurality of interface boards. Each interface board includes a DSD connector for connecting a DSD to the interface board and a backplane connector for connecting to a backplane for communicating with a respective computing unit. In one aspect, the at least one interface module includes a housing and a plurality of openings in a side of the housing with each opening configured to receive a respective interface board. A plurality of guide member pairs is positioned to guide respective interface boards when inserted into respective openings such that the backplane connector is located at a respective predetermined location for connecting to the backplane. In another aspect, the interface boards are removable from the interface module.

A system for testing a semiconductor may include a transfer chamber, at least one loadlock chamber and at least one test chamber. The transfer chamber may include a plurality of sidewalls. The loadlock chamber may be arranged on a first sidewall of the sidewalls of the transfer chamber. The loadlock chamber may include a carrier configured to receive a plurality of wafers. The test chamber may be arranged on a second sidewall of the sidewalls of the transfer chamber. When the transfer chamber is connected to the loadlock chamber, a pressure of the transfer chamber may be changed into a pressure of the loadlock chamber. When the transfer chamber is connected to the test chamber, the pressure of the transfer chamber may be changed into a pressure of the test chamber.

A wafer inspection apparatus according to one embodiment is a wafer inspection apparatus including a plurality of inspection parts arranged in a height direction and a lateral direction, and includes a pair of air circulating means disposed at both ends in a longitudinal direction of an air circulating region including the plurality of inspection parts arranged in the lateral direction and configured to circulate air in the circulating region.

Provided is a semiconductor inspection device capable of high-speed response analysis as defect analysis of a fine-structured device constituting an LSI. Therefore, the semiconductor inspection device includes a vacuum chamber 3, a sample table 4 which is disposed in the vacuum chamber and on which a sample 6 is placed, an electron optical system 1 disposed such that an electron beam is emitted from above the sample, a plurality of probe units 24 connected to external devices 11 and 12 disposed outside the vacuum chamber via a coaxial cable 10, and an electrode 5 provided on or in the vicinity of the sample table. The probe unit 24 includes a measurement probe 8 configured to come into contact with the sample, a GND terminal 9 configured to come into contact with the electrode 5, and a probe holder 7 configured to hold the measurement probe and the GND terminal, connect a signal line of the coaxial cable to the measurement probe, and connect a GND line of the coaxial cable to the GND terminal. When the measurement probe of the probe unit comes into contact with the sample, the GND terminal comes into contact with the electrode.

Techniques are described herein that are capable of progressively thermally drying a quantum circuit. An inert gas is progressively heated by a heater element to provide a heated inert gas. Heated ambient air and the heated inert gas combine in a heating channel, causing a combination of the heated ambient air and the heated inert gas to flow into a probe compartment to progressively thermally dry a quantum circuit therein. A flow rate of the inert gas is controlled to cause the combination to have a relative humidity less than or equal to a threshold. A temperature of the heater element may be controlled to be approximately equal to a progressively increasing target temperature within a tolerance of 3.0° C. Heating of the inert gas may be initiated based on detection of the inert gas, and the flow and heating of the inert gas may be automatically discontinued.

Examples disclosed herein relate to a on-chip or built-in self-test (BIST) module for an RFIC including means to up-convert a signal from a test frequency to RF at an input to the RFIC and down-convert and output signal.