Patent classifications
G01R31/2877
TEST SOCKET ASSEMBLIES WITH LIQUID COOLED FRAME FOR SEMICONDUCTOR INTEGRATED CIRCUITS
A socket assembly with liquid cooling frame for a semiconductor integrated circuit (IC) chip is provided. The socket assembly includes a liquid cooling socket frame including a metallic frame body defining an opening sized to receive the semiconductor IC chip, wherein the frame body includes one or more channels transversely positioned through the frame body and positioned in an interior of the frame body, the channels defining a fluid path. The socket assembly also includes a socket cartridge including a metallic cartridge body defining a plurality of cavities each sized to receive a test probe therein, the socket frame covering a portion of the socket cartridge and exposing the plurality of cavities at the opening.
Test carrier and electronic component testing apparatus
A test carrier that accommodates a DUT and includes a first flow passage through which fluid supplied from an outside of the test carrier flows.
Multi-input multi-zone thermal control for device testing
Disposing a DUT between a cold plate and an active thermal interposer device of the thermal management head. The DUT includes a plurality of modules and the active thermal interposer device includes a plurality of zones, each zone of the plurality of zones corresponding to a respective module of the plurality of modules and operable to be selectively heated. Receiving a respective set of inputs corresponding to each zone of the plurality of zones. Performing thermal management of the plurality of modules of the DUT by separately controlling temperature of each zone of the plurality zones by controlling a supply of coolant to a cold plate, and individually controlling heating of each zone of the plurality zones.
Semiconductor package test system and semiconductor package fabrication method using the same
A semiconductor package test system includes a test pack on which a semiconductor package is loaded, and a semiconductor package testing apparatus. The semiconductor package testing apparatus includes a receiving section that receives the test pack. The receiving section includes a pack receiving slot into which the test pack is inserted. The test pack includes a chuck on which the semiconductor package is fixed, a probe block disposed above the chuck, and a connection terminal. The receiving section includes a receiving terminal that is electrically connected to the connection terminal when the receiving terminal contacts the connection terminal. The probe block includes at least one needle configured to be electrically connected to the semiconductor package disposed on the chuck upon the chuck moving toward the semiconductor package. The receiving section is provided in plural.
SYSTEM AND METHOD FOR CONTROLLING REFRIGERATION LOOP EXPANSION VALVE FLOW AND COMPRESSOR SPEED UNDER CONDITIONS OF RAPID HEAT LOAD CHANGES
A hybrid controller for a thermal control unit for controlling the temperature of a device under test (DUT) is described that uses information from an in independent heat-injecting control loop as a fast-responding proxy for relative changes in DUT test head load. This information provides additional feedback to the refrigeration sub-system's controller(s), resulting in achieving the overall system goal of temperature control of the DUT over a wide range of set point temperatures and the rapidly changing DUT head load.
THERMAL ARRAY WITH GIMBAL FEATURES AND ENHANCED THERMAL PERFORMANCE
Embodiments of the present invention provide testing systems with liquid cooled thermal arrays that can pivot freely in three dimensions allowing surfaces to be brought into even, level, and secure contact, thereby preventing air gaps between surfaces and improving thermal performance. In this way, more DUTs can be tested in parallel within a small test space, overall costs of the test system are reduced, and greater cooling capacity can be provided for testing high-powered devices. Gimbaled mounts are disposed on a bottom surface of individual thermal interface boards (TIBs) of a test system, and/or on top of individual thermal heads of a thermal array (TA) having a common cold plate (or having multiple cold plates).
TEST CARRIER AND ELECTRONIC COMPONENT TESTING APPARATUS
A test carrier that accommodates a DUT and includes a first flow passage through which fluid supplied from an outside of the test carrier flows.
THERMAL SOLUTION FOR MASSIVELY PARALLEL TESTING
An apparatus for thermal control of a device under test (DUT) includes a cooling structure operable to provide cooling, the cooling structure operable to inlet cooling material via an inlet port thereof and operable to outlet cooling material via an outlet port thereof, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, and a heater layer operable to generate heat based on an electronic control, and wherein the VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. A thermal interface material layer is disposed on the heater layer. The thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT. The apparatus includes a compression mechanism for providing compression to the VTCM layer to vary a thermal conductance of the VTCM layer. The compression mechanism is also for decoupling the VTCM layer from the heater layer.
Cryogenic Wafer Testing System
Cryogenic testing systems for testing electronic components such as wafers under cryogenic conditions are provided. The novel designs enable fast throughput by use of a cryogenically maintained test surface to which wafers may be rapidly introduced, cooled, and manipulated to contact testing elements while maintaining high quality cryogenic conditions. Thermal shielding is achieved by floating shields and/or flexible bellows that provide effective thermal shielding of the test environment while enabling manipulation of wafers with a wide range of motion. Also provided are novel door assemblies, chuck configurations, and vacuum plate bases that enable effective maintenance of cryogenic conditions and high throughput.
Cryogenic wafer test system
One example includes a cryogenic wafer test system. The system includes a first chamber that is cooled to a cryogenic temperature and a wafer chuck confined within the first chamber. The wafer chuck can be configured to accommodate a wafer device-under-test (DUT) comprising a plurality of superconducting die. The system also includes at least one wafer prober configured to implement a test on a superconducting die of the plurality of superconducting die via a plurality of electrical probe contacts. The system further includes a wafer chuck actuator system confined within a second chamber. The wafer chuck actuator system can be configured to provide at least one of translational and rotational motion of the wafer chuck to facilitate alignment and contact of a plurality of electrical contacts of the superconducting die to the respective plurality of electrical probe contacts of the at least one wafer prober.