An apparatus and a method for inspecting a semiconductor includes a water tank which includes a housing, an interior of which is filled with a liquid, and a support block which provides a settling surface for an inspection object inside the housing. A plurality of signal generators are installed on a bottom surface of the housing, and output a frequency signal in a direction in which the inspection object is located. A power supply operates the signal generators. A probe is placed above the inspection object, and a receiver which operates with the probe and is attached to a bottom surface of the support block. Foreign matter remaining on the inspection object are removed, using a plurality of frequency signals which are output by the plurality of signal generating units.

A testing system for testing an image sensor, includes a probe card, a pogo block receiving output signals of the probe card, an interface board configured to receive output signals of the pogo block, convert the received output signals of the pogo block, and output the converted signals through a cable, and a testing apparatus connected to the interface board through the cable. The testing apparatus is configured to test the device under test through signals received through the cable. The interface board includes an active interface module configured to amplify the received output signals of the pogo block, convert the amplified signals into signals having a same frequency as the received output signals of the pogo block, and transmit the converted signals to the cable.

The present disclosure relates to a method and a corresponding circuit for the fault detection of an electrical circuit, wherein the electrical circuit includes a first inductive interface, at least a first branch, and a second branch, wherein the first and the second branches are connected in parallel, wherein the first branch includes two parallel and counter-currently-connected diodes, and wherein the first and second branches are connected to the first inductive interface. The method includes applying an alternating voltage or an alternating current across the first inductive interface via a second inductive interface, wherein the applied voltage or current is low enough that essentially no current flows through either the first or the second diode; measuring the impedance across the first inductive interface via the second inductive interface; and determining whether a fault is present in the second branch.

An electrical property testing device of an evaluation board includes a main circuit board, a voltage detecting unit, a storing unit, a processing unit and an adapter board. The voltage detecting unit is configured to detect a plurality of voltage values of the signal pads. The storing unit stores a plurality of standard voltage values corresponding to the signal pads. The processing unit is electrically connected to the voltage detecting unit and the storing unit. The processing unit receives the voltage values and determines whether the voltage values match the standard voltage values to generate a determining result. The adapter board includes a plurality of conductive pads. The conductive pads are correspondingly connected to the signal pads of the evaluation board. The voltage detecting unit detects the voltage values of the signal pads of the evaluation board via the conductive pads.

A semiconductor device for testing a semiconductor wafer includes a circuit board, a probe disposed below the circuit board and facing the semiconductor wafer, an integrated substrate disposed between the circuit board and the probe, and signal-transmitting module disposed on the circuit board and next to the integrated substrate. The probe is electrically coupled to the circuit board through the integrated substrate, and the signal-transmitting module transmits a test signal to the probe through the integrated substrate and the circuit board to perform a test to the semiconductor wafer. Another semiconductor device including the integrated substrate and a manufacturing method thereof are provided.

A contact socket module for use in an automated test equipment (ATE) for testing electronic components (DUTs) being carried by a carrier comprises: a plurality of groups of spring contacts, wherein each spring contact comprises a DUT sided contact tip, a retracting plate being moveable, and a controller controlling the movement of the retracting plate, wherein the retracting plate and the spring contacts act mechanically on each other. In a first position the DUT sided contact tips are adapted to contact to contact portions of the electronic components, and in a second position, the DUT sided contact tips are adapted to release the contact to the contact portions of the electronic components.

The present disclosure provides a semiconductor testing apparatus with a connected unit, which is applied to a wafer probing testing or a final testing. The semiconductor testing apparatus comprises a semiconductor testing printed circuit board, a functional module and the connected unit. First contact points are disposed on a first surface of the semiconductor testing printed circuit board, and electrically connected to the functional module. Second contact points are disposed on a second surface of the semiconductor testing printed circuit board, and electrically connected to a functional controller. The first contact points and the second contact points have independent and non-interfering working time domains. Therefore, the present disclosure can utilize the area of the semiconductor testing printed circuit board, and can independently perform functional testing of a wafer or packaged integrated circuit devices using multiple time domains, in a multi-time domain, synchronous or asynchronous manner.

An example probe for a test system includes a conductor to carry direct current (DC) signals between a DC testing resource and a signal trace on the test system, where the signal trace is for carrying the DC signals and alternating current (AC) signals to and from a device under test; and an inductor connected in series with the conductor. A mechanism is included in the probe for enabling the conductor to move toward the signal trace or a pin electrically connected to the signal trace to create an electrical connection between the conductor and the signal trace to enable the testing resource to transmit the DC signals to the signal trace, and to move away from the signal trace or the pin so that no electrical connection is created between the conductor and the signal trace when the DC signals are not to be transmitted to the signal trace.

An intermediate connecting member according to one aspect of the present disclosure is provided between a first member including multiple first terminals and a second member including multiple second terminals. The intermediate connecting member includes multiple connection parts configured to electrically connect the first terminals to the second terminals, and a retainer holding the multiple connection parts. Each of the multiple connection parts is formed of an elastic member to which an electrically conductive property is given at least on a surface of the elastic member.

An apparatus for thermal control of a device under test (DUT) includes a cooling structure operable to provide cooling, the cooling structure operable to inlet cooling material via an inlet port thereof and operable to outlet cooling material via an outlet port thereof, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, and a heater layer operable to generate heat based on an electronic control, and wherein the VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. A thermal interface material layer is disposed on the heater layer. The thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT. The apparatus includes a compression mechanism for providing compression to the VTCM layer to vary a thermal conductance of the VTCM layer. The compression mechanism is also for decoupling the VTCM layer from the heater layer.