A probe head for a testing apparatus integrated on a semiconductor wafer is disclosed having a first plurality of contact probes having a first transversal diameter, a second plurality of micro contact probes having a second transversal diameter, smaller than the first transversal diameter, and a flexible membrane having conductive tracks for connecting a first plurality contact probe with a corresponding second plurality micro contact probe. The second plurality contact probes are arranged between the testing apparatus and the flexible membrane, and the second plurality micro contact probes are arranged between the flexible membrane and a semiconductor wafer. The second plurality micro contact probes are configured to abut onto contact pads of a device under test integrated in the semiconductor wafer, with each first plurality contact probe being in contact with a corresponding second plurality micro contact probe through a conductive track of the flexible membrane to connect the device under test with the testing apparatus.

A method is provided for in situ functionality testing of electrical switches using a Functional Reflectometry Test (FRT) of switches on the signal path of electrical circuits in a semiconductor interface. The method includes initiating the functionality testing of the electrical switches in situ, wherein the functionality of the electrical switches is tested while the electrical switches are connected to the Automatic Test Equipment (ATE) and are in-use testing semiconductors. The method also includes conducting full Functional Reflectometry Testing of the electrical switches in situ in an open switch state and a closed switch state to determine whether each of the electrical switches is one of fully functional, stuck closed, and stuck open, wherein testing for each state is performed as a single vector functional test to minimize test time overhead.

A hybrid automated testing equipment (ATE) system can simultaneously test electrical and optical components of a device under test, such as an optical transceiver. The device under test can be a multilane optical transceiver that transmits different channels of data on different lanes. The hybrid ATE system can include one or more light sources and optical switches in an optical test lane selector to selectively test and calibrate each optical and electrical components of each lane of the device under test.

A board-like connector, a dual-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-arm bridges spaced apart from each other and an insulating layer. Each of the dual-arm bridges includes a carrier, a first cantilever, a second cantilever, a first abutting column, and a second abutting column, the latter two of which extend from the first and second cantilevers along two opposite directions. The first cantilever and the second cantilever extend from and are coplanar with the carrier. The insulating layer connects the carriers of the dual-arm bridges. The first abutting column and second abutting column of each of the dual-arm bridges respectively protrude from two opposite sides of the insulating layer, and are configured to abut against two boards, respectively.

A testing apparatus for Data Storage Devices (DSDs) includes a chassis and at least one interface module configured to be removably inserted into the chassis and house a plurality of interface boards. Each interface board includes a DSD connector for connecting a DSD to the interface board and a backplane connector for connecting to a backplane for communicating with a respective computing unit. In one aspect, the at least one interface module includes a housing and a plurality of openings in a side of the housing with each opening configured to receive a respective interface board. A plurality of guide member pairs is positioned to guide respective interface boards when inserted into respective openings such that the backplane connector is located at a respective predetermined location for connecting to the backplane. In another aspect, the interface boards are removable from the interface module.

A testing substrate includes a first build-up structure and a ceramic substrate. The ceramic substrate is arranged on the first build-up structure. The first bonding interface between the first build-up structure and the ceramic substrate includes a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface. A manufacturing method of a testing substrate and a probe card are also provided.

A testing substrate includes a substrate and a first build-up structure. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first conductive pattern. The first conductive pattern includes a plurality of conductive connectors, and each conductive connector penetrates the substrate from the first surface to the second surface of the substrate. The first build-up structure is arranged on the first surface. The first build-up structure has a second conductive pattern. The first conductive pattern is electrically connected to the second conductive pattern, and the size of the first conductive pattern is larger than or equal to the size of the second conductive pattern. A manufacturing method of the testing substrate and a probe card are also provided.

A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.

An image test system includes a test assembly and an image capture card. The test assembly is provided for obtaining a test signal from a test object, and includes an interface conversion circuit for converting signal transmission form of the test signal. The image capture card is provided for obtaining the test signal from the test assembly, and obtaining an image data from the test signal. The image test system further includes a test signal clock generation circuit for obtaining a test signal clock from the test signal, or the image capture card further includes a pair of clock input pins for obtaining the test signal clock directly from the test object.