A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.

The invention relates to a method, an apparatus and a non-transitory computer-readable storage medium for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) when loading and executing a function of a runtime library, to include: receiving a request to drive a General-Purpose Input/Output (GPIO) interface (I/F), which includes a parameter required for completing a Joint Test Action Group (JTAG) command; issuing a first hardware instruction to the GPIO I/F to set a register corresponding to a GPIO test data input (TDI) pin according to the parameter carried in the request for emulating to issue the JTAG command to a solid-state disk (SSD) device, wherein the single-board PC is coupled to the SSD device through the GPIO I/F; issuing a second hardware instruction to the GPIO I/F to read a value of the register corresponding to the GPIO TDI pin; and replying with a completion message in response to the request.

System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

A device may generate, using a random telegraph signal (RTS) noise generator, a simulated RTS noise as input to a transistor included in an electronic circuit. The device may determine, based on the simulated RTS noise input to the transistor, a simulated output signal from the transistor.

A simulation method and system of verifying an operation of a semiconductor memory device of a memory module at a design level. The simulation method includes setting a configuration and an arrangement of a registered clock driver (RCD) and a configuration and an arrangement of first semiconductor memory devices to fourth semiconductor memory devices, on a printed circuit board (PCB) through a graphic user interface (GUI). When a RCD test execution command is applied through the GUI, executing a test program to apply control signals to control signal terminals of the PCB based on a command truth table, to compare the applied control signals and control signals output through first driver output terminals of the RCD, and to create an RCD test result. When the RCD operates normally, performing a test on the memory module.

A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

The present application relates to a circuit simulation test method and apparatus, a device, and a medium. The method includes: creating a parametric data model, wherein the parametric data model is configured to generate preset write data based on a preset parameter; creating a test platform, wherein the test platform is configured to generate a test result based on the preset write data; creating an eye diagram generation module, wherein the eye diagram generation module is configured to generate a data eye diagram based on the test result; and conducting a simulation test, inputting the preset write data to the test platform and obtaining the test result, and generating the data eye diagram by using the eye diagram generation module.

The present disclosure describes a method for analyzing signal waveforms produced by integrated circuits. The method includes determining characteristic points of a control signal, and each characteristic point includes a corresponding time value and represents an edge change of the control signal. The method also includes determining sets of data sampling points. Each set of data sampling points is located between adjacent characteristic points of the characteristic points. The method further includes obtaining data values of a signal waveform, and a data value of the signal waveform is obtained at a data sampling point of the sets of data sampling points. The method further includes obtaining data values of a reference waveform, and a data value of the reference waveform is obtained at the data sampling point and determining a difference between the data value of the signal waveform and the data value of the reference waveform.