A method for protecting a reconfigurable digital integrated circuit includes multiple parallel processing channels each comprising an instance of a functional logic block and an error detection unit, the method comprising the successive steps of: activating the error detection unit in order to detect an error in at least one processing channel, executing the data replay mechanism, and then activating the error detection unit in order to detect an error in at least one processing channel, if an error is detected again, executing a self-test on each processing channel, for each processing channel, if the self-test does not detect any error, executing the data replay mechanism for this processing channel, if the self-test detects an error, reconfiguring that part of the configuration memory associated with this processing channel.

Integrated circuit devices, systems, and circuitry are provided to perform signal tests on a device under test. One such integrated circuit device may include memory having instructions to generate a number of test streams to send to a device under test and a testbench processor. The testbench processor may generate the test streams based on the instructions using thread execution circuitry that switches context based on context identifiers corresponding to respective test streams.

A method for performing verification and testing of a device under test (DUT) is described. The method includes receiving, by a processing device, inputs from a user regarding a hardware design for the DUT. The processing device presents cover group attribute suggestions to the user based on the hardware design and receives cover group information from the user corresponding to one or more cover group attributes of one or more cover groups based on the cover group attribute suggestions. Based on the cover group information, the processing device automatically generates verification code, including one or more cover group definitions.

An error rate measuring apparatus includes a data transmission unit that transmits a test signal of a known pattern and a parameter value defined by a communication standard to a device under test, and a bit error measurement unit that measures a bit error of a signal transmitted from the device under test. The data transmission unit sequentially changes the parameter value and transmits the parameter value to the device under test. The bit error measurement unit measures a bit error of a signal transmitted from the device under test corresponding to the parameter value. The error rate measuring apparatus further includes a discrimination unit that discriminates a parameter value at which the number of bit errors is the least in a measurement result of the bit error measurement unit, as an optimum value of emphasis of an output waveform of the device under test.

It is possible to know a guideline for adjusting the levels of three voltage thresholds of a PAM4 signal. An error detection device receives a measurement pattern including a pseudo random pattern having equal appearance frequencies of four levels, decodes the measurement pattern into a most significant bit sequence signal MSB and a least significant bit sequence signal LSB, based on three voltage thresholds Vth1, Vth2, and Vth3, identifies and counts, by a level counting unit, the four levels of the measurement pattern, based on the most significant bit sequence signal MSB and the least significant bit sequence signal LSB, and displays numerical values or bar graphs indicating ratios of the appearance frequencies of the four levels of the measurement pattern so as to be in the same order as waveform levels of the measurement pattern, based on a result of the counting.

It is possible to know a guideline for adjusting the levels of three voltage thresholds of a PAM4 signal. An error detection device receives a measurement pattern including a pseudo random pattern having equal appearance frequencies of four levels, decodes the measurement pattern into a most significant bit sequence signal MSB and a least significant bit sequence signal LSB, based on three voltage thresholds Vth1, Vth2, and Vth3, identifies and counts, by a level counting unit, the four levels of the measurement pattern, based on the most significant bit sequence signal MSB and the least significant bit sequence signal LSB, and displays numerical values or bar graphs indicating ratios of the appearance frequencies of the four levels of the measurement pattern so as to be in the same order as waveform levels of the measurement pattern, based on a result of the counting.

A method of generating a simulation model based on simulation data and measurement data of a target includes classifying weight parameters, included in a pre-learning model learned based on the simulation data, as a first weight group and a second weight group based on a degree of significance, retraining the first weight group of the pre-learning model based on the simulation data, and training the second weight group of a transfer learning model based on the measurement data, wherein the transfer learning model includes the first weight group of the pre-learning model retrained based on the simulation data.

A test and measurement circuit including a capacitor in parallel with a device under test, a direct current voltage source configured to charge the capacitor, a pulse generator configured to generate a pulse for testing the device under test, and a sensor for determining a current in the device under test.

A ground fault detection circuit can include a band-pass filter that can have a first node and a second node that can be coupled to an earth ground. The first node can be coupled to a local ground of an automatic test equipment (ATE) system for an electrical device that can be coupled via at least one wire to the ATE. The band-pass filter can be configured to pass and amplify a test current signal established at the first node in response to a coupling of one of a conductor of the at least one wire carrying the test current signal to the local ground, and a conductive element of the electrical device carrying the test current signal to the local ground. A fault alert signal can be provided to provide an indication of ground fault based on a comparison of the amplified test current signal.

A high-frequency coaxial attenuator includes a first coaxial cable portion that includes a first center conductor having a first length, and a first insulator of the first length formed around the first center conductor, wherein the first center conductor and the first insulator form a first diameter. A second coaxial cable portion is separated from the first coaxial cable portion by a gap. The second coaxial cable portion includes a second center conductor having a second length, and a second insulator of the second length formed around the second center conductor. A semiconductor material is deposited in the gap between the first coaxial cable portion and the second coaxial cable portion. The semiconductor material may be configured to provide an impedance of 500Ω and provides 20 dB of attenuation, and a 10:1 voltage divider based on a 50Ω input impedance of test equipment.