In one example case, a cross-platform system includes a first automated test platform having a first test instrument and a first glue layer interface that exposes test functions to direct testing by the first test instrument. The system further includes a second automated test platform having a second test instrument and a second glue layer interface that exposes the same test functions to direct testing by the second test instrument. In the system, the glue layers abstract the respective and different control commands used by the different, first and second test instruments. Using the glue layers, the same higher-level test code can be executed by the control computers of both the first and second automated test platforms.

A test board includes a first board and a second board. The first board includes a socket on which a device under test (DUT) is mounted, and a first functional circuit. The first functional circuit exchanges signals and data with the DUT in an actual operating environment of the DUT, and performs a first test on the DUT using a first test signal. The first test signal is identical to a signal to be transmitted in the actual operating environment. The second board includes a processor and a multiplexer. The processor performs a second test different from the first test on the DUT using a second test signal. The second test signal is different from the first test signal and checks an electrical characteristic of the DUT itself. The multiplexer selects one of the first test signal and the second test signal to transmit to the DUT.

The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

A method for operating a test apparatus including a plurality of shared resources is shown, wherein the plurality of shared resources can be used in different instruments. The method includes blocking a first set of resource blockers when a first instrument, which requires a first subset of the shared resources, is to be executed. Furthermore, the method tries to block a second set of resource blockers, when a second instrument, which requires a second subset of the shared resources, is to be executed. Therefore, the first set of resource blockers is different from the second set of resource blockers and a plurality of resource blockers are assigned to a shared resource, which is involved in a conflicting combination of instruments and in a non-conflicting combination of instruments.

A system and method for testing electronic circuit devices. The system has a central processing unit with a plurality of separate core processing units. The utility service program is initiated at the startup of the computer program which acts as an intermediary between user applications and the computer operating system. The utility service is responsive to an ATE execution engine to set an affinity for one or more processing cores for exclusive use for the ATE execution engine. The ATE execution engine communicates with the utility service to reserve one or more processing cores for execution of the program for testing electronic devices.

Systems and methods for testing and/or operating remote devices are disclosed. The embodiments provide cost-effective, convenient, and flexible means for the sensing and/or probing of remote devices. Signals generated by remote devices may be received, analyzed, logged, and displayed, i.e., enhancements to the functionalities of an oscilloscope are achieved. Signals to remote devices may be provided, i.e. enhancements to the functionalities of a wave generator, logic analyzers, bus analyzers, and the like are achieved. More particularly, enhancements to the operability, capabilities, and functionality of such previously available testing equipment, are provided, via the operation of a remote, portable, and lightweight test bed. The test bed may be operated and controlled remotely via a user-computing device. The test bed senses, probes, and/or controls a remote device and test data is generated and/or acquired. The test data is provided to the user-computing device for analysis, visualization, and test report generation.

A method for testing using an automated test equipment is presented. The method comprises transmitting instructions for performing an automated test from a system controller to a tester processor, wherein the instructions comprise parameters for a descriptor module. The method also comprises programming a reconfigurable circuit for implementing the descriptor module onto an instantiated FPGA block coupled to the tester processor. Further, the method comprises interpreting the parameters from the descriptor module using the reconfigurable circuit, wherein the parameters control execution of a plurality of test operations on a DUT coupled to the instantiated FPGA block. Additionally, the method comprises constructing at least one packet in accordance with the parameters, wherein each one of the at least one packet comprises a command for executing a test operation on the DUT. Finally, the method comprises performing a handshake with the DUT to route the at least one packet to the DUT.

A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

Systems and methods for testing printed circuit boards (PCBs) are disclosed herein. In one embodiment, a tester for printed circuit boards (PCBs) includes a test fixture having a plurality of electrical contacts for contacting the PCBs that are units under test (UUTs). The test fixture carries a remote test peripheral master (RTPM) module, and a remote test peripheral slave (RTPS) module. The RTPM module and the RTPS module are connected through a remote test peripheral (RTP) bus.

A measurement system for measuring a device under test is described. The measurement system includes a control and analysis module composed of one or more circuits, a stimulus module composed of one or more circuits, and a measurement interface composed of ,for example, one or more circuits. The stimulus module is configured to generate an electric stimulus signal based on predefined measurement parameters. The measurement system is configured to be connected to a device under test via the measurement interface. The measurement interface is configured to forward the electric stimulus signal from the stimulus module to the device under test. The measurement interface further is configured to forward a response signal from the device under test to the control and analysis module, wherein the response signal corresponds to a response of the device under test to the stimulus signal. The control and analysis module is configured to analyze the response signal, thereby generating a set of analysis data. The control and analysis module is further configured to compare the set of analysis data generated with a database. The database includes several measurement data sets being associated with different classes or types of devices under test. The control and analysis module is further configured to adapt the predefined measurement parameters of the stimulus module based on the comparison of the set of analysis data with the database. Further, a method of measuring a device under test is described.