Patent classifications
G01R31/31903
METHOD AND APPARATUS FOR CONFIGURING SUB ROUTE FLOW, STORAGE MEDIUM, AND EQUIPMENT
A sub route flow is a route flow different from a main route flow in testing of a semiconductor product. A method for configuring a sub route flow includes: determining at least one test item of the semiconductor product; obtaining a first test template corresponding to the test item, wherein the first test template includes preset test parameters; displaying the preset test parameters; receiving test parameters adjusted according to the preset test parameters; configuring current test parameters of the test item according to the adjusted test parameters; and forming the sub route flow of the semiconductor product according to the current test parameters of the test item.
Integrated circuit test apparatus
An integrated circuit test apparatus includes: a first test unit configured to output a current for a built-in self test (BIST) progress state for each internal circuit of an integrated circuit in a BIST test mode and to determine whether each internal circuit operates normally in a wake-up mode of the integrated circuit; and a first determination module configured to determine whether each internal circuit is in a stuck state based on a change detected by the first test unit.
Debug system providing debug protection
A debug system includes a chip to be tested and a debug controller. The chip to be tested includes a circuit to be tested, a debug access circuit and a debug protection circuit. When a protection function is not enabled, the debug protection circuit enables a communication between the debug access circuit and the chip to be tested, the debug controller accesses the data of the chip to be tested via the debug access circuit for debugging the circuit to be tested. When the protection function is enabled, the debug protection circuit blocks the communication between the debug access circuit and the chip to be tested, the debug controller transmits a message to the debug protection circuit via the debug access circuit, and the debug protection circuit determines whether to disable the protection function according to the message.
Measurement device and method for measuring a device under test
A measurement device is described that comprises a measurement unit configured to perform measurements on an electric signal of a device under test while applying at least one measurement parameter for performing the measurements. The measurement device has an integrated direct current source configured to power the device under test. The measurement device also comprises a monitoring unit configured to monitor at least one monitoring parameter of the direct current source. The measurement device has a control unit configured to control the measurement parameter. Further, a method for measuring a device under test is described.
TERMINAL APPARATUS, BASE STATION APPARATUS, COMMUNICATION METHOD, AND INTEGRATED CIRCUIT
Provided is a technique related to a terminal apparatus, a base station apparatus, a communication system, a communication method, and an integrated circuit that are capable of efficiently performing device-to-device communication. In a case where a terminal apparatus capable of direct communication between terminal apparatuses starts a timer corresponding to a group index that identifies short-range group communication, to which the terminal apparatus belongs, and the timer expires, switching is performed from a first radio resource allocation method, by which a radio resource to be used for the direct communication is requested to a base station apparatus, to a second radio resource allocation method by which the terminal apparatus selects a radio resource to be used for the direct communication.
SCHEDULER
Embodiments provide a scheduler for scheduling test times of a plurality of tester software environments for an automatic test equipment. The scheduler is configured to automatically assign test times to the plurality of tester software environments, to acquire test instructions from a tester software environment of the plurality of tester software environments to which a current test time is assigned, to control the automatic test equipment to perform a test according to the test instructions in order to obtain test results, and to provide the test results to the tester software environment of the plurality of tester software environments to which the current test time is assigned.
DEBUG SYSTEM PROVIDING DEBUG PROTECTION
A debug system includes a chip to be tested and a debug controller. The chip to be tested includes a circuit to be tested, a debug access circuit and a debug protection circuit. When a protection function is not enabled, the debug protection circuit enables a communication between the debug access circuit and the chip to be tested, the debug controller accesses the data of the chip to be tested via the debug access circuit for debugging the circuit to be tested. When the protection function is enabled, the debug protection circuit blocks the communication between the debug access circuit and the chip to be tested, the debug controller transmits a message to the debug protection circuit via the debug access circuit, and the debug protection circuit determines whether to disable the protection function according to the message.
SYSTEMS, METHODS, AND DEVICES FOR HIGH-SPEED INPUT/OUTPUT MARGIN TESTING
A margin testing device includes at least one interface structured to connect to a device under test (DUT) one or more controllers structured to create a set of test signals based on a sequence of pseudo random data and one or more pre-defined parameters, and an output structured to send the set of test signals to the DUT. Methods and a system for testing a DUT with the disclosed margin tester and other testing device are also described.
Measurement system and method for testing a device under test
A measurement system for testing a device under test is described, with at least two antennas, at least two reflectors, a signal generation and/or analysis equipment and a test location. Each of the antennas is assigned to a corresponding reflector. Each of the antennas is configured to transmit/receive an electromagnetic signal so that a beam path is provided between the respective antenna and the test location. The electromagnetic signal is reflected by the respective reflector so that the electromagnetic signal corresponds to a planar wave. The beam paths have different angular orientations that are adjustable. At least one antenna and the corresponding reflector are coupled with each other so that an integrated beam path adjustment unit is established including at least one antenna and the corresponding reflector. Further, a testing method is described.
Configurable integrated logic analyzer
Methods and systems for collecting operational data from a target digital system are disclosed. In some embodiments, a method includes determining a test configuration to be used to configure a probe circuit. Determining the test configuration may include selecting one or more signal sources, defining one or more signal patterns within the selected signal sources, and defining one or more trigger events associated with the one or more signal patterns. Based on the test configuration, the probe circuit selects input/output (I/O) channels for a test cycle and captures one or more traces from the selected I/O channels during the test cycle.